MDT10P65

This specification are subject to be changed without notice. Any latest information

please preview http;//www.mdtic.com.tw

P. 6

2005/10

Ver. 1.6

00

Indirect addressing register

01

Timer0 register

02

Program counter low byte

03

Status register

Bit 0 : Carry

1 : Digit carry

2 : Zero flag

3 : Power-down

4 : WDT time-out

5 : Register bank select (For direct addressing)

=0 Bank 0 (00h-7Fh)

=1 Bank 1 (80h-FFh)

7-6 : Always read as zero.

04

Memory select register

05

Port A data register

06

Port B data register

07

Port C data register

08

Port D data register

09

Port E data register

Bit 2-0 – Port E data register.

7-3 – Unimplemented. Always set as 0.

0A

Program memory segment register

0B

Interrupt control register

Bit 0 – PB port change interrupt flag bit.

1 – PB0/IRQ external interrupt flag bit.

2 – Timer0 overflow interrupt flag bit.

3 – PB port change interrupt enable bit.

4 – PB0/IRQ external interrupt enable bit.

5 – Timer0 overflow interrupt enable bit.

6 – Peripheral interrupt enable bit.

7 – Global interrupt enable bit.

0C

Peripheral interrupt flag register 1.

Bit 0 – Timer1 overflow interrupt flag bit

7-1 – Unimplemented. Always read as 0.

0D

Peripheral interrupt flag register 2.

Bit 6-0 – Unimplemented. Read as zero.

7 – PD port change interrupt flag bit

0E

Timer1 data register low byte.