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SP9602KS Datasheet(PDF) 3 Page - Sipex Corporation |
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SP9602KS Datasheet(HTML) 3 Page - Sipex Corporation |
3 / 11 page SP9602DS/02 SP9602 Dual, 12-Bit, Low Power Voltage Output D/A Converter © Copyright 1999 Sipex Corporation 3 0 CODE 4095 INLE, DNLE Plots +0.25 lsb DNLE -0.25 lsb +0.25 lsb INLE -0.25 lsb SPECIFICATIONS (continued) (Typical at 25˚C, T MIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS STABILITY Gain 15 ppm/˚C t MIN to tMAX Bipolar Zero 15 ppm/˚C t MIN to tMAX SWITCHING CHARACTERISTICS t DS Data Set Up Time 140 100 ns to rising edge of WR1 t DN Data Hold Time 0 ns Figure 4 t WR Write Pulse Width 140 100 ns t XFER Transfer Pulse Width 140 ns t WC Total Write Command 280 200 ns POWER REQUIREMENTS Note 5 V DD +5V, +3%; Note 4, 5 –J, –K 1.6 2.5 mA V SS –5V, +3%; Note 4, 5 –J, –K 1.6 2.5 mA Power Dissipation 16 mW ENVIRONMENTAL AND MECHANICAL Operating Temperature -J, -K 0 +70 °C Storage -60 +150 °C Packages –_N 28–pin Plastic DIP –_S 28–pin SOIC Notes: 1. Integral Linearity, for the SP9602, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition. 2. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 3. 1 LSB = 2*V REF/4,096. 4. V REF = 0V. 5. The following power up sequence is recommended to avoid latch up: VSS (-5V), VDD (+5V), REFIN. |
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