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AS4LC2M8S1-8TC Datasheet(PDF) 8 Page - Alliance Semiconductor Corporation |
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AS4LC2M8S1-8TC Datasheet(HTML) 8 Page - Alliance Semiconductor Corporation |
8 / 29 page ® 5/21/01; v.1.1 Alliance Semiconductor P. 8 of 29 AS4LC2M8S1 AS4LC1M16S1 AC parameters common to all waveforms Sym Parameter CAS latency –7 –8 –10 Unit Notes Min Max Min Max Min Max tAC CLK to valid output delay 3– 5.5 – 6 – 6 ns 6 2– 8.5 – 7 – 6 ns 6,8 1 – 18 – 22 – 22 ns 6,8 tAH Address hold time – 1 – 1 – 1 ns 7 tAS Address setup time 2 – 2 – 2 – ns 7 tBDL Last data-in to burst stop 0 – 0 – 0 – tCK 9 tCCD Read/write command to read/write command 1– 1 – 1 – tCK 9 tCDL Last data-in to new column address delay 1– 1 – 1 – tCK 9 tCH CLK high-level width 2.75 – 3 – 3 – ns 7 tCK CLK cycle time 3 7 1000 8 1000 10 1000 ns 10 2 8.7 1000 10 1000 12 1000 ns 10 1 20 1000 25 1000 25 1000 ns 10 tCKED CKE to CLOCK disable or power-down entry mode 1– 1 – 1 – tCK tCKH CKE hold time 1 – 1 – 1 – ns tCKS CKE setup time 2 – 2 – 2 – ns tCL CLK low-level width 2.75 – 3 – 3.5 – ns 7 tCMH CS, RAS, CAS, WE, DQM hold time 1– 1 – 1 – ns tCMS CS, RAS, CAS, WE, DQM setup time 2– 2 – 2 – ns tDAL Data-in to ACTIVE command 35 – 5 – 5 – tCK 5,11 25 – 5 – 5 – tCK 5,11 14 – 4 – 4 – tCK 5,11 tDH Data in hold time 1 – 1 – 1 – ns tDPL Data in to PRECHARGE 2 – 2 – 2 – tCK 12 tDQD DQM to input data delay 1 – 1 – 1 – tCK 9 tDQM DQM to data mask during writes 0– 0 – 0 – tCK 9 tDQZ DQM to data high Z during reads 2– 2 – 2 – tCK 9 tDS Data in setup time 2 – 2 – 2 – ns tDWD Write command to input data delay 0– 0 – 0 – tCK 9 tHZ Data-out high-impedance time 3– 5.5 – 6 – 9 ns 13 2– 8.5 – 9 – 9 ns 13 1 – 18 – 22 – 22 ns 13 tLZ Data-out low-impedance time 1– 1 – 1 – ns |
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