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AS4LC2M8S1 Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation |
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AS4LC2M8S1 Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation |
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9 / 29 page  ® AS4LC2M8S1 AS4LC1M16S1 5/21/01; v.1.1 Alliance Semiconductor P. 9 of 29 Notes 1IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 2 Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 3 Address transitions average one transition every two-clock period. 4The IDD current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-latency is reduced. 5tCK = 7 ns for –7, 8 ns for –8, and 10 ns for –10. 6If clock tr > 1 ns, (tr/2 – 0.5)ns should be added to the parameter. 7If clock (tr and tf) > 1 ns, [(tr + tf)/2 – 1] ns should be added to the parameter. 8VIH overshoot: VIH(max) = VDDQ + 2V for a pulse width ≤ 3 ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL(min) = –2V for a pulse width ≤ 3 ns and the pulse width cannot be greater than one third of the cycle rate. 9 Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter. 10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR and PRECHARGE commands). CKE may be used to reduce the data rate. 11 Timing actually specified tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 12 Timing actually specified by tWR. 13 tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going to HIGH-Z. 14 CLK must be toggled a minimum of two times during this period. 15 Enables on-chip refresh and address counters. 16 All voltages referenced to VSS. 17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0 ° C ≤ T A ≤ 70° C) is endured. tMRD Load mode register to active/refresh command 2– 2 – 2 – tCK 5 tOH Output data hold time @ 30 pF 32 – 2.5 – 3 – ns 6 22 – 2.5 – 3 – ns 6 12 – 2.5 – 3 – ns 6 tPED CKE to CLOCK enable or power-down exit mode 1– 1 – 1 – tCK tRAS Active to precharge command 42 120,000 48 120,000 50 120,000 ns tRC Active command period 70 – 80 – 80 – ns 8 tRCAR Auto refresh period 70 – 80 – 80 – ns tRCD Active to read or write delay 33 – 3 – 3 – tCK 8 tREF Refresh period—2048 rows –64 – 64 – 64 ms tROH Data-out high Z from precharge/burst stop command 33 – 3 – 3 – tCK 9 22 – 2 – 2 – tCK 9 11 – 1 – 1 – tCK 9 tRP Precharge command period 33 – 3 – 3 – tCK 8 tRRD Active Bank A to Active Bank B command 14 – 16 – 20 – ns tT Transition time 0.3 1.0 0.3 1.0 0.3 1.0 ns tWR WRITE recovery time 2 –2 – 2 – tCK tXSR Exit SELF REFRESH to ACTIVE command 70 – 80 – 80 – ns 20 Sym Parameter CAS latency –7 –8 –10 Unit Notes Min Max Min Max Min Max |
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