6.42

6

IDT71T016SA, 2.5V CMOS Static RAM

1 Meg (64K x 16-Bit)

Commercial and Industrial Temperature Ranges

NOTES:

1. A write occurs during the overlap of a LOW

CS, LOW BHE or BLE, and a LOW WE.

2.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the

CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

NOTES:

1.

WE is HIGH for Read Cycle.

2. Address must be valid prior to or coincident with the later of

3. Transition is measured ±200mV from steady state.

ADDRESS

OE

CS

5326 drw 07

(3)

(3)

(3)

DATA

VALID

OUT

BHE, BLE

ACS

(3)

(2)

(2)

ADDRESS

CS

5326 drw 08

(5)

(5)

(5)

(2)

WE

PREVIOUS DATA VALID

DATA VALID

(5)

(3)