2Mx36 & 4Mx18 DDR II SIO b2 SRAM

K7J643682M

K7J641882M

- 6 -

Rev 1.0

Aug. 2005

The K7J643682M and K7J641882M are 75,497,472-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs.

They are organized as 2,097,152 words by 36bits for K7J643682M and 4,194,304 words by 18 bits for K7J641882M.

The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports.

Memory bandwidth is higher than DDR sram without separate input output as separate read

and write ports eliminate bus turn around cycle.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read data are referenced to echo clock ( CQ or CQ ) outputs.

Read address and write address are registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and late write enable high speed operations.

Simple depth expansion is accomplished by using LD for port selection.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7J643682M and K7J641882M are implemented with SAMSUNG's high performance 6T CMOS technology

and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K insted of C and C.

When the LD is disabled after a read operation, the K7J643682M and K7J641882M will first complete

burst read operation before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.

Address is presented and stored in the write address register synchronized with next K clock.

For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.

The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.

Next burst data is transfered and registered synchronous with following K clock rising edge.

Continuous write operations are initated with K rising edge.

And "late writed" data is presented to the device on every rising edge of both K and K clocks.

When the LD is disabled, the K7J643682M and K7J641882M will enter into deselect mode.

The device disregards input data presented on the same cycle W disabled.

The K7J643682M and K7J641882M support byte write operations.

Write Operations