2Mx36 & 4Mx18 DDR II SIO b2 SRAM

K7J643682M

K7J641882M

- 8 -

Rev 1.0

Aug. 2005

Notes: 1. X means "Don

′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

↑ ).

3. Assumes a WRITE cycle was initiated.

4. This table illustates operation for x18 devices.

K

K

OPERATION

↑

L

L

WRITE ALL BYTEs ( K

↑ )

↑

L

L

WRITE ALL BYTEs ( K

↑ )

↑

L

H

WRITE BYTE 0 ( K

↑ )

↑

L

H

WRITE BYTE 0 ( K

↑ )

↑

H

L

WRITE BYTE 1 ( K

↑ )

↑

H

L

WRITE BYTE 1 ( K

↑ )

↑

H

H

WRITE NOTHING ( K

↑ )

↑

H

H

WRITE NOTHING ( K

↑ )

Notes: 1. X means "Don

′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (

↑ ).

3. Assumes a WRITE cycle was initiated.

K

K

OPERATION

↑

LLLL

WRITE ALL BYTEs ( K

↑ )

↑

LLLL

WRITE ALL BYTEs ( K

↑ )

↑

L

H

H

H

WRITE BYTE 0 ( K

↑ )

↑

L

H

H

H

WRITE BYTE 0 ( K

↑ )

↑

H

L

H

H

WRITE BYTE 1 ( K

↑ )

↑

H

L

H

H

WRITE BYTE 1 ( K

↑ )

↑

H

H

L

L

WRITE BYTE 2 and BYTE 3 ( K

↑ )

↑

H

H

L

L

WRITE BYTE 2 and BYTE 3 ( K

↑ )

↑

HHHH

WRITE NOTHING ( K

↑ )

↑

HHHH

WRITE NOTHING ( K

↑ )

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

Notes: 1. X means "Don

′t Care".

2. The rising edge of clock is symbolized by (

↑ ).

3. Before enter into clock stop status, all pending read and write operations will be completed.

K

LD

R/W

D

Q

OPERATION

D(A0)

D(A1)

Q(A0)

Q(A1)

Stopped

X

X

Previous state

Previous state

Previous state

Previous state

Clock Stop

↑

H

X

X

X

High-Z

High-Z

No Operation

↑

LH

X

X

Read

↑

L

L

Din at K(t+1)

Din at K(t+1)

High-Z

High-Z

Write