Rev 1.4

1Mx36 & 2Mx18 SRAM

- 9 -

Oct. 2005

K7D321874A

K7D323674A

TRUTH TABLE

NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".

- K & K are complementary.

K

B1

B2

B3

DQ

Operation

↑

H

L

X

Hi-Z

No Operation, Pipeline High-Z

↑

L

H

H

DOUT

Load Address, Single Read

↑

L

H

L

DOUT

Load Address, Double Read

↑

L

L

H

DIN

Load Address, Single Write

↑

L

L

L

DIN

Load Address, Double Write

↑

H

H

X

B

Increment Address, Continue

Interleaved Burst

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0

0

1

1

0

1

0

1

0

0

1

1

1

0

1

0

1

1

0

0

0

1

0

1

1

1

0

0

1

0

1

0

BURST SEQUENCE TABLE

Linear Burst Mode

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0

0

1

1

0

1

0

1

0

1

1

0

1

0

1

0

1

1

0

0

0

1

0

1

1

0

0

1

1

0

1

0

OUTPUT TRISTATE TRUTH TABLE

K

Operation

DQ (n)

DQ (n+1)

↑

Write (B2=L)

X

High-Z

↑

Deslect (NOP) (B1=H, B2=L)

X

High-Z