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DS90C387R Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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DS90C387R Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 28 page AC Timing Diagrams (Continued) 10128825 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 12) + ISI (Inter-symbol interference) (Note 13) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 12: Cycle-to-cycle jitter is less than 150 ps at 85 MHz Note 13: ISI is dependent on interconnect length; may be zero FIGURE 11. Receiver Skew Margin 10128827 FIGURE 12. TJCC Test Setup - DS90C387R 10128828 FIGURE 13. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter www.national.com 10 |
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