4

®

SHC804

INSTALLATION

GROUNDING AND BYPASSING

SHC804 has four COMMON pins (pins 10, 15, 21 and 23)

and all must be tied together and connected to the system

analog common (V

possible. It is preferable to have a large ground plane

surrounding the sample/hold and have all four common pins

soldered directly to it. Note that the metal case is internally

connected to pin 23; therefore, care must be taken to avoid

a ground loop if the case is allowed to contact the ground

plane.

Most digital return currents pass through pin 10. Noise from

the switch-drive circuit may couple directly into the main op

amp summing junction, a very noise-sensitive node. Care

must be taken to insure that no voltage differences occur

between pin 10 and the other common pins. This is the

reason pin 10 must be connected directly to the ground

plane.

For the same reason, the logic supply should be kept as free

of noise as possible.

±V

internally bypassed to common with 0.01

µF capacitors. It is

recommended that the user install additional external 0.1

µF

to 1

µF tantalum bypass capacitors at each supply pin.

SAMPLE/HOLD CONTROL

A TTL logic “0” at pin 11 (or a logic “1” at pin 12) switches

the SHC804 into the Sample (track) mode. In this mode, the

device acts as a unity-gain inverting amplifier, the output

following the inverse of the input. A logic “1” at pin 11 (or

a logic “0” at pin 12) will switch the SHC804 into the Hold

mode. The output voltages will be held constant at the value

present when the Hold command is given.

If pin 11 is used, pin 12 must be connected to the DCOM

(pin 10). If pin 12 is used, pin 11 must be tied to V

the HOLD and HOLD inputs as logic function may ad-

versely affect the charge offset (pedestal). A clean digital

signal (no overshoot) at the HOLD of HOLD inputs will

also reduce charge offset errors. Pins 11 and 12 present less

than one standard TTL load (two LSTTL loads) to the digital

drive circuit.

DISCUSSION OF

SPECIFICATIONS

Throughput Nonlinearity is defined as total Hold mode,

nonadjustable, input to output error caused by charge offset,

gain nonlinearity, droop, feedthrough, and thermal tran-

sients. It is the inaccuracy due to these errors which cannot

be corrected by Offset and Gain adjustments.

Gain Error is the difference between the input and output

voltage magnitude (in the Sample mode) due to the amplifier

gain errors.

Droop Rate is the voltage decay at the output when in the

Hold mode due to storage capacitor and FET switch leakage

current and the input bias current of the output amplifier.

Feedthrough is the amount of output voltage change caused

by an input voltage change when the sample/hold is in the

Hold mode.

Aperture Delay Time is the time required to switch from

Sample to Hold. The time is measured from the 50% point

of the Hold mode control transition to the time at which the

output stops tracking the input.

Aperture Uncertainty Time is the nonrepeatability of aper-

ture delay time.

Acquisition Time is the time required for the sample/hold

output to settle to within a given error band of its final value

when the sample/hold is switched from Hold to Sample.

Charge Offset (Pedestal) is the output voltage change that

results from charge coupled into the Hold capacitor through

the gate capacitance of the switching field effect transistor.

This charge appears as an offset at the output.

Sample-to-Hold Switching Transient is the switching tran-

sient which appears on the output when the sample/hold is

switched from Sample to Hold. Both the magnitude and the

settling time of the transient are specified.

OPERATION

In the Sample (track) mode the circuit acts as a unity-gain

inverting amplifier. In the Hold mode, the capacitor, C

holds the value of the output at the time the unit was

switched to the Hold mode. Additional circuits compensate

for switching transients and provide switch leakage current

cancellation. The amplifier provides high current drive and

low output impedance to external loads.

GAIN, OFFSET, CHARGE OFFSET

SHC804 has been internally-trimmed to eliminate the need

for external trim potentiometers for Gain, Offset (in Sample

mode) and Charge Offset (Pedestal). System Gain and Off-

set errors can be adjusted elsewhere in the system, at an

input amplifier preceding the sample/hold, or at an analog-

to-digital converter following the sample/hold.

Droop

V

OUT

Acquisition

Time

Sample

Hold

V

IN

Sample-to-Hold

Transient

V

t

FIGURE 1. Definition of Acquisition Time, Droop and

Sample-to-Hold Transient.