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RX5005H Datasheet(PDF) 6 Page - RF Monolithics, Inc |
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RX5005H Datasheet(HTML) 6 Page - RF Monolithics, Inc |
6 / 10 page RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-8148 E-mail: info@rfm.com Page 6 of 10 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 http://www.rfm.com ©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc. RX5005H-100405 threshold, or squelch, offsets the comparator’s slicing level from 0 to 90 mV, and is set with a resistor between the RREF and THLD1 pins. This threshold allows a trade- off between receiver sensitivity and output noise density in the no-signal condition. For best sensitivity, the threshold is set to 0. In this case, noise is output continuously when no signal is present. This, in turn, requires the circuit being driven by the RXDATA pin to be able to process noise (and signals) continuously. This can be a problem if RXDATA is driving a circuit that must “sleep” when data is not present to conserve power, or when it its necessary to minimize false interrupts to a multitasking processor. In this case, noise can be greatly reduced by increasing the threshold level, but at the expense of sensitivity. The best 3 dB bandwidth for the low-pass filter is also affected by the threshold level setting of DS1. The bandwidth must be increased as the threshold is increased to minimize data pulse-width variations with sig- nal amplitude. Data slicer DS2 can overcome this compromise once the signal level is high enough to enable its operation. DS2 is a “dB-below- peak” slicer. The peak detector charges rapidly to the peak value of each data pulse, and de- cays slowly in between data pulses (1:1000 ratio). The slicer trip point can be set from 0 to 120 mV below this peak value with a resistor between RREF and THLD2. A threshold of 60 mV is the most common setting, which equates to “6 dB below peak” when RFA1 and RFA2 are running a 50%-50% duty cycle. Slicing at the “6 dB-below-peak” point reduces the signal amplitude to data pulse-width variation, allowing a lower 3 dB filter bandwidth to be used for improved sensitivity. DS2 is best for ASK modulation where the transmitted waveform has been shaped to minimize signal bandwidth. However, DS2 is subject to being temporarily “blinded” by strong noise pulses, which can cause burst data errors. Note that DS1 is active when DS2 is used, as RXDATA is the logical AND of the DS1 and DS2 outputs. DS2 can be disabled by leaving THLD2 disconnected. A non-zero DS1 threshold is required for proper AGC oper- ation. AGC Control The output of the Peak Detector also provides an AGC Reset signal to the AGC Control function through the AGC comparator. The purpose of the AGC function is to extend the dynamic range of the receiver, so that the re- ceiver can operate close to its transmitter when running ASK and/or high data rate modulation. The onset of saturation in the output stage of RFA1 is detected and generates the AGC Set signal to the AGC Control function. The AGC Control function then selects the 5 dB gain mode for RFA1. The AGC Comparator will send a reset signal when the Peak Detector output (multiplied by 0.8) falls below the threshold voltage for DS1. A capacitor at the AGCCAP pin avoids AGC “chattering” during the time it takes for the signal to propagate through the low-pass filter and charge the peak detector. The AGC capacitor also allows the hold-in time to be set longer than the peak detector decay time to avoid AGC chattering during runs of “0” bits in the received data stream. Note that AGC operation re- quires the peak detector to be functioning, even if DS2 is not being used. AGC operation can be defeated by connecting the AGCCAP pin to Vcc. The AGC can be latched on once engaged by connecting a 150 kilohm re- sistor between the AGCCAP pin and ground in lieu of a capacitor. Receiver Pulse Generator and RF Amplifier Bias The receiver amplifier-sequence operation is controlled by the Pulse Gen- erator & RF Amplifier Bias module, which in turn is controlled by the PRATE and PWIDTH input pins, and the Power Down (sleep) Control Sig- nal from the Bias Control function. In the low data rate mode, the interval between the falling edge of one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse tPRI is set by a resistor between the PRATE pin and ground. The interval can be adjust- ed between 0.1 and 5 µs. In the high data rate mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the start-to-start period tPRC for ON pulses to RFA1 are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs. In the low data rate mode, the PWIDTH pin sets the width of the ON pulse tPW1 to RFA1 with a resistor to ground (the ON pulse width tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in the low data rate mode). The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs. However, when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifiers are controlled by the PRATE resistor as described above. Both receiver RF amplifiers are turned off by the Power Down Control Sig- nal, which is invoked in the sleep mode. Receiver Mode Control The receiver operating modes – receive and power-down (sleep), are con- trolled by the Bias Control function, and are selected with the CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0 both high place the unit in the receive mode. Setting CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs must be held at a logic level; they cannot be left unconnected. Receiver Event Timing Receiver event timing is summarized in Table 1. Please refer to this table for the following discussions. Turn-On Timing The maximum time tPR required for the receive function to become opera- tional at turn on is influenced by two factors. All receiver circuitry will be op- erational 5 ms after the supply voltage reaches 2.2 Vdc. The BBOUT- CMPIN coupling-capacitor is then DC stabilized in 3 time constants (3*tBBC). The total turn-on time to stable receiver operation for a 10 ms power supply rise time is: tPR = 15 ms + 3*tBBC Sleep and Wake-Up Timing The maximum transition time from the receive mode to the power-down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0 are both low (1 µs fall time). The maximum transition time tSR from the sleep mode to the receive mode is 3*tBBC, where tBBC is the BBOUT-CMPIN coupling-capacitor time con- stant. When the operating temperature is limited to 60 oC, the time required to switch from sleep to receive is dramatically less for short sleep times, as less charge leaks away from the BBOUT- CMPIN coupling capacitor. AGC Timing The maximum AGC engage time tAGC is 5 µs after the reception of a -30 dBm RF signal with a 1 µs envelope rise time. The minimum AGC hold-in time is set by the value of the capacitor at the AGCCAP pin. The hold-in time tAGH = CAGC/19.1, where tAGH is in µs and CAGC is in pF. |
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