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TB62201AFG Datasheet(PDF) 53 Page - Toshiba Semiconductor |
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TB62201AFG Datasheet(HTML) 53 Page - Toshiba Semiconductor |
53 / 89 page TB62201AFG 2005-04-04 53 STROBE Signal, Internal CR CLK, and Output Current Waveform (When STROBE signal is input in SLOW DECAY MODE) When STROBE signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next CR-CLK timing. Because of this, compared with a method in which the counter is not reset, response to the input data is faster. (The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform: 1.25 µs @ 100 kHz CHOPPING.) When the C-CLK counter is reset due to STROBE signal input, CHARGE MODE is entered momentarily due to current comparison. Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison. MDT RNF NF Set current value Set current value STROBE signal input Iout fchop fchop fchop 37.5% MIXED DECAY MODE MDT RNF Momentarily enters CHARGE MODE Reset CR-CLK counter here |
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