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PI6C410MAAE Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6C410MAAE Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 21 page  1 PS8736C 12/19/05 Features • 14.318 MHz Crystal Input • Selectable of 100, 133, 166, 200, 266, 333, and 400 MHz CPU Output Frequencies • SMBus: Power Management Control • Spread Spectrum support (-0.5% down spread) • Packaging (Pb-free & Green available): — 56-Pin TSSOP Output Features • Two Pairs of Differential CPU Clocks • One selectable of CPU/SRC Clock • Seven Pairs of SRC Clocks • Six PCI Clocks • One 48 MHz USB clock • One REF clock • One 96 MHz Differential clock Description PI6C410M is a high-speed, low-noise clock generator designed to work with the Intel Mobile PCI Express Chipset. This Spread Spectrum PLL based clock generator reduces EMI emission and supports a wide range of frequencies. Jitter Performance • < 85ps Cycle-to-Cycle CPU 0/1 clock jitter • < 125ps Cycle-to-Cycle CPU 2 clock jitter • < 350ps Cycle-to-Cycle 48 MHz clock jitter • < 500ps Cycle-to-Cycle PCI clock jitter • < 125ps Cycle-to-Cycle SRC clock jitter • < 1000ps Cycle-to-Cycle REF clock jitter Skew Performance • < 100ps Output-to-output CPU 0/1 clock skew • < 150ps Output-to-output CPU 2 clock skew • < 500ps Output-to-output PCI clock skew • < 250ps Output-to-output SRC clock skew Block Diagram Pin Configuration PI6C410M/410MA Clock Generator for Intel PCI Express Mobile Chipset PCI_2 PCI_STOP# CPU_STOP# FS_C / TEST_SEL REF VSS_REF XTAL_IN XTAL_OUT VDD_REF SDA SCL VSS_CPU CPU_0 CPU_0# VDD_CPU CPU_1 CPU_1# IREF VSS_A VDD_A CPU2_ITP / SRC7 CPU2_ITP# / SRC7# VDD_SRC SRC_6 SRC_6# SRC_5 SRC_5# VSS_SRC VDD_PCI VSS_PCI PCI_3 PCI_4 PCI_5 VSS_PCI VDD_PCI PCIF_0 / ITP_EN PCIF_1 VTT_PWRGD# / PWRDWN VDD_48 USB_48/FS_A VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE SRC_0 SRC_0# SRC_1 SRC_1# VDD_SRC SRC_2 SRC_2# SRC_3 SRC_3# SRC_4 SRC_4# VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PLL 1 C O N T R O L USB_48 / FS_A FS_B / TEST_MODE VTT_PWRGD# / PWRDWN Div Div Div FS_C / TEST_SEL PCI_STOP# CPU_STOP# XTAL OSC SMBus Logic REF DOT_96 DOT 96# USB_48 / FS_A XTAL_IN XTAL_OUT SDA SCL PLL 2 /2 PCIF_0 / ITP_EN PCI [2:5] PCIF[0:1] SRC [0:6] SRC [0:6]# CPU[0:1] CPU[0:1]# CPU2_ITP / SRC7 CPU2_ITP# / SRC7# |
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