WCSN0436V1P

Document #: 38-05246 Rev. **

Page 3 of 14

Pin Definitions

Pin Number

Name

I/O

Description

50–44,

81–82, 99,

100, 32–37

Input-

Synchronous

Address Inputs used to select one of the 131,072 address locations. Sampled at

the rising edge of the CLK.

96–93

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the

88

WE

Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active

LOW. This signal must be asserted LOW to initiate a write sequence.

85

ADV/LD

Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new

address. When HIGH (and CEN is asserted LOW) the internal burst counter is

advanced. When LOW, a new address can be loaded into the device for an access.

After being deselected, ADV/LD should be driven LOW in order to load a new

address.

89

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified

with CEN. CLK is only recognized if CEN is active LOW.

98

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

97

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

92

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

86

OE

Input-

Asynchronous

Output Enable, active LOW. Combined with the synchronous logic block inside the

device to control the direction of the I/O pins. When LOW, the I/O pins are allowed

to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act

as input data pins. OE is masked during the data portion of a write sequence, during

the first clock when emerging from a deselected state, when the device has been

deselected.

87

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-

nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since

deasserting CEN does not deselect the device, CEN can be used to extend the

previous cycle when required.

29–28,

25–22,

19–18,

13–12, 9–6,

3–2, 79–78,

75–72,

69–68, 63–62

59–56, 53–52

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained

read cycle. The direction of the pins is controlled by OE and the internal control

logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,

three-stated during the data portion of a write sequence, during the first clock when

emerging from a deselected state, and when the device is deselected, regardless

of the state of OE.

30, 1, 80 51

I/O-

Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to

31

MODE

Input Strap pin

Mode Input. Selects the burst order of the device. Tied HIGH selects the inter-

leaved burst order. Pulled LOW selects the linear burst order. MODE should not

change states during operation. When left floating MODE will default HIGH, to an

interleaved burst order.

15, 16, 41, 65,

66, 91

Power Supply

Power supply inputs to the core of the device. Should be connected to 3.3V power

supply.

4, 11, 14, 20,

27, 54, 61, 70,

77

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.