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WCSN0436V1P-143AC Datasheet(PDF) 11 Page - Weida Semiconductor, Inc.

Part # WCSN0436V1P-143AC
Description  128Kx36 Pipelined SRAM with NoBL TM Architecture
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Manufacturer  WEIDA [Weida Semiconductor, Inc.]
Direct Link  http://www.weida.com.my/website/
Logo WEIDA - Weida Semiconductor, Inc.

WCSN0436V1P-143AC Datasheet(HTML) 11 Page - Weida Semiconductor, Inc.

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WCSN0436V1P
Document #: 38-05246 Rev. **
Page 11 of 14
Switching Waveforms (continued)
ADV/LD
CLK
ADDRESS
CE
Data-
In/Out
tCYC
tCH tCL
tALS
tALH
RA1
tAH
tAS
tCES t
CEH
tCO
Q1
= DON’T CARE
= UNDEFINED
The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table).
Out
tCLZ
tDOH
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Device
originally
deselected
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
WA2
Q1+1
Out
Q1+2
Out
Q1+3
Out
RA3
tCLZ
tCHZ
D2+1
In
D2+2
In
D2+3
In
D2
In
tCO
Q3
Out
tDS
tDH
Burst Sequences
BWS[3:0]
tWS tWH
WE
tWS tWH
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.


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