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WCMC8016V9X Datasheet(PDF) 1 Page - Weida Semiconductor, Inc. |
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WCMC8016V9X Datasheet(HTML) 1 Page - Weida Semiconductor, Inc. |
1 / 12 page ADVANCE INFORMATION 8Mb (512K x 16) Pseudo Static RAM WCMC8016V9X WeidaSemiconductor, Inc. 38-14026 Revised August 2003 Features • Wide voltage range: 2.70V–3.30V • Access Time: 70ns • Ultra-low active power — Typical active current: 2.0mA @ f = 1 MHz — Typical active current: 11mA @ f = fmax • Ultra low standby power • Easy memory expansion with CE, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Offered in a 48 Ball BGA Package Functional Description[1] The WCMC8016V9X is a high-performance CMOS pseudo static RAM organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life ® (MoBL ®) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption by more than 99% when deselected using CE LOW, CE2 HIGH or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH, CE2 LOW OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling even when the chip is selected (Chip Enable CE LOW, CE2 HIGH and both BHE and BLE are LOW). Reading from the device is accomplished by asserting the Chip Enables (CE LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes Logic Block Diagram Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress .com. 512K x 16 RAM Array I/O0–I/O7 COLUMN DECODER DATA IN DRIVERS OE I/O8–I/O15 WE BLE BHE Power -Down Circuit A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE2 CE 1T |
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