XC61F

Series

161

2

■Marking

GSOT-23, SOT-89

SOT-23

(TOP VIEW)

SOT-89

(TOP VIEW)

q w er

q

w

e

r

q Represents the integer of the Detect Voltage and the Output Configuration

CMOS output (XC61FC series)

N-channel open drain (XC61FN series)

VOLTAGE (V)

CMOS

N-ch

CMOS

N-ch

CMOS

N-ch

CMOS

N-ch

CMOS

N-ch

CMOS

N-ch

CMOS

N-ch

w Represents the decimal number of the Detect Voltage

e Indicates the presence of delay time

r Represents the assembly lot no.

Based on internal standards

6

80 to 400ms

7

1 to 50ms

H

DESIGNATOR

CONFIGURATION

A

B

VOLTAGE (V)

K

L

S

M

C

D

E

F

CONFIGURATION

DESIGNATOR

N

P

R

DESIGNATOR

0

1

q

.4

3

4

2

q

.0

q

.1

q

.2

DESIGNATOR

5

6

7

8

9

VOLTAGE (V)

q

.7

q

.3

q

.8

q

.9

VOLTAGE (V)

q

.5

q

.6

DESIGNATOR

50 to 200ms

5

DELAY TIME

GTO-92

2 3 4 5

6 7

1

TO-92（L Type）

(TOP VIEW)

61C

L

2 3 4 5

6 7

1

TO-92（T Type）

(TOP VIEW)

61C

q Represents the output

configuration

DESIGNATOR OUTPUT CONFIGURATION

C

CMOS

N

N-ch

w Re

w

3

5

D

r Indicates Delay Time

DESIGNATOR

DELAY TIME

1

50ms∼200ms

5

1ms∼50ms

4

80ms∼400ms

DESIGNATOR

DETECT VOLTAGE ACCURACY

2

within

±2%

t Represents the Detect Voltage Accuracy

w Represents the Detect Voltage

w

3

3.3

5

5.0

e

DESIGNATOR

VOLTAGE（V）

3

0

y Represents a least significant digit of

the produced year 

DESIGNATOR PRODUCED YEAR

0

2000

1

2001

u Denotes the production lot number

0 to 9, A to Z repeated(G.I.J.O.Q.W excepted)

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