162

2

■Block Diagram

■Electrical Characteristics

Vref

Delay Circuit

Vref

Delay Circuit

(1)CMOS output

(2)N-channel open drain output

■絶対最大定格

Ta=25℃

SYMBOL

RATINGS

UNITS

12

V

50

mA

∼ 9

V

Continuous Total

SOT-23

Pd

150

mW

Power Dissipation

SOT-89

500

Topr

-30

∼ +80

O

C

Tstg

-40

∼ +125

O

C

Output Voltage

PARAMETER

Output Current

Input Voltage

Storage Temperature

Operating Ambient Temperature

CMOS

N-ch open drain

TO-92

300

■Absolute Maximum Ratings

Ta＝25℃

Note : The power consumption during power-start to output being stable (release operation) is 2

µA greater than it is after that period

(completion of release operation) because of delay circuit through current.

* Transient Delay Time : 1ms to 50ms & 80ms to 400ms versions are also available.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CIRCUIT

Detect Voltage

V

x 0.98

x 1.02

Hysteresis Range

V

x 0.02

x 0.05

x 0.08

0.9

2.6

=2.0V

1.0

3.0

Supply Current

=3.0V

1.3

3.4

µA

2

1

1

=4.0V

1.6

3.8

=5.0V

2.0

4.2

Operating Voltage

0.7

10.0

V

1

N-ch

2.2

=2.0V

7.7

3

=3.0V

10.1

Output Current

=4.0V

11.5

mA

=5.0V

13.0

P-ch

-10.0

4

( CMOS output )

Detect Voltage

± 100

ppm/

°C

-

Temperature Characteristics

Transient Delay Time

tDLY *

50

200

ms

5

0.6V to 10V

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