3D7220

MONOLITHIC 10-TAP

FIXED DELAY LINE

(SERIES 3D7220)

FEATURES

•

All-silicon, low-power CMOS technology

•

TTL/CMOS compatible inputs and outputs

•

Vapor phase, IR and wave solderable

•

Auto-insertable (DIP pkg.)

•

Low ground bounce noise

•

Leading- and trailing-edge accuracy

•

Delay range: 0.75ns through 7000ns

•

Delay tolerance: 2% or 0.5ns

•

Temperature stability:

±2% typical (-40C to 85C)

•

Vdd stability:

±1% typical (4.75V-5.25V)

•

Minimum input pulse width: 15% of total delay

•

14-pin Gull-Wing available as drop-in

replacement for hybrid delay lines

FUNCTIONAL DESCRIPTION

The 3D7220 10-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 0.75ns through 700ns. The

input is reproduced at the outputs without inversion, shifted in time as

per the user-specified dash number. The 3D7220 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

The all-CMOS 3D7220 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is

offered in a standard 14-pin auto-insertable DIP and space saving

surface mount 14-pin SOIC and 16-pin SOL packages.

PACKAGES

14

13

12

11

10

9

8

1

2

3

4

5

6

7

IN

N/C

O2

O4

O6

O8

GND

VDD

O1

O3

O5

O7

O9

O10

3D7220-xx

DIP

3D7220G-xx Gull-Wing

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IN

N/C

N/C

O2

O4

O6

O8

GND

VDD

N/C

O1

O3

O5

O7

O9

O10

3D7220S-xx SOL

1

2

3

4

5

6

7

14

13

12

11

10

9

8

IN

N/C

O2

O4

O6

O8

GND

VDD

O1

O3

O5

O7

O9

O10

3D7220D-xx SOIC

PIN DESCRIPTIONS

IN

Delay Line Input

O1

Tap 1 Output (10%)

O2

Tap 2 Output (20%)

O3

Tap 3 Output (30%)

O4

Tap 4 Output (40%)

O5

Tap 5 Output (50%)

O6

Tap 6 Output (60%)

O7

Tap 7 Output (70%)

O8

Tap 8 Output (80%)

O9

Tap 9 Output (90%)

O10

Tap 10 Output (100%)

VDD +5 Volts

GND Ground

For mechanical dimensions, click

here.

For package marking details, click

here.

TABLE 1: PART NUMBER SPECIFICATIONS

TOLERANCES

INPUT RESTRICTIONS

DASH

NUMBER

TOTAL

DELAY (ns)

TAP-TAP

DELAY (ns)

Rec’d Max

Frequency

Absolute Max

Frequency

Rec’d Min

Pulse Width

Absolute Min

Pulse Width

-.75

6.75

± 0.5*

0.75

± 0.4

28.4 MHz

166.7 MHz

17.6 ns

3.00 ns

-1

9.0

± 0.5*

1.0

± 0.5

23.8 MHz

166.7 MHz

21.0 ns

3.00 ns

-1.5

13.5

± 0.5*

1.5

± 0.7

18.0 MHz

166.7 MHz

27.8 ns

3.00 ns

-2

18.0

± 0.5*

2.0

± 0.8

14.5 MHz

166.7 MHz

34.5 ns

3.00 ns

-2.5

22.5

± 0.5*

2.5

± 1.0

12.1 MHz

125.0 MHz

41.2 ns

4.00 ns

-4

36.0

± 0.7*

4.0

± 1.3

8.33 MHz

133.3 MHz

60.0 ns

6.00 ns

-5

50.0

± 1.0

5.0

± 1.5

6.67 MHz

66.7 MHz

75.0 ns

7.50 ns

-10

100.0

± 2.0

10.0

± 2.0

3.33 MHz

33.3 MHz

150 ns

15.0 ns

-20

200.0

± 4.0

20.0

± 4.0

1.67 MHz

16.7 MHz

300 ns

30.0 ns

-50

500.0

± 10

50.0

± 10

0.67 MHz

6.67 MHz

750 ns

75.0 ns

-100

1000

± 20

100

± 20

0.33 MHz

3.33 MHz

1500 ns

150 ns

-700

7000

± 140

700

± 140

0.05 MHz

0.48 MHz

10500 ns

1050 ns

* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns

± 1.0ns

NOTE:

Any dash number between .75 and 700 not shown is also available as standard.

2005 Data Delay Devices

Doc #03004

DATA DELAY DEVICES, INC.

1

4/15/05

3 Mt. Prospect Ave. Clifton, NJ 07013