3D3418 datasheet(3/7 Pages) DATADELAY

Part #	3D3418

Description	MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3418 - LOW NOISE)

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Manufacturer	DATADELAY [Data Delay Devices, Inc.]

Direct Link	http://www.datadelay.com

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3 / 7 page

3D3418

Doc #02006

DATA DELAY DEVICES, INC.

3

10/28/02

3 Mt. Prospect Ave. Clifton, NJ 07013

APPLICATION NOTES (CONT’D)

The flexible 3D3418 architecture can be

exploited to conform to these more demanding

user-dictated accuracy constraints. However, to

facilitate production and device identification, the

part number will include a custom reference

designator identifying the user requested

accuracy specifications and operating conditions.

It is strongly recommended that the

engineering staff at DATA DELAY DEVICES

be consulted.

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly

dependent on power supply and temperature.

The monolithic 3D3418 programmable delay line

utilizes novel and innovative compensation

circuitry to minimize the delay variations induced

by fluctuations in power supply and/or

temperature.

The thermal coefficient is reduced to 600

PPM/C, which is equivalent to a variation, over

the 0C-70 C operating range, of

±3% from the

room-temperature delay settings. The power

supply coefficient is reduced, over the 3.0V-

3.6V operating range, to

±1% of the delay

settings at the nominal 3.3VDC power supply

and/or

±2ns, whichever is greater.

It is essential that the power supply pin be

adequately bypassed and filtered. In addition,

the power bus should be of as low an

impedance construction as possible. Power

planes are preferred.

PROGRAMMED DELAY (ADDRESS)

UPDATE

A delay line is a memory device. It stores

information present at the input for a time equal

to the delay setting before presenting it at the

output with minimal distortion. The 3D3418 8-bit

programmable delay line can be represented by

256 serially connected delay elements

(individually addressed by the programming

data), each capable of storing data for a time

equal to the device increment (step time). The

delay line memory property, in conjunction with

the operational requirement of “instantaneously”

connecting the delay element addressed by the

programming data to the output, may inject

spurious information onto the output data stream.

In order to ensure that spurious outputs do not

occur, it is essential that the input signal be idle

(held high or low) for a short duration prior to

updating the programmed delay. This duration is

given by the maximum programmable delay.

Satisfying this requirement allows the delay line

to “clear” itself of spurious edges. When the new

address is loaded, the input signal can begin to

switch (and the new delay will be valid) after a

time given by tPDV or tEDV (see section below).

PROGRAMMED DELAY (ADDRESS)

INTERFACE

Figure 1 illustrates the main functional blocks of

the 3D3418 delay program interface. Since the

3D3418 is a CMOS design, all unused input pins

must be returned to well defined logic levels,

VCC or Ground.

TRANSPARENT PARALLEL MODE

(MD = 1, AE = 1)

The eight program pins P0 - P7 directly control

the output delay. A change on one or more of

the program

pins will be reflected on the output delay after a

time tPDV, as shown in Figure 2. A register is

required if the programming data is bused.

LATCHED PARALLEL MODE

(MD = 1, AE PULSED)

The eight program pins P0 - P7 are loaded by the

falling edge of the Enable pulse, as shown in

Figure 3. After each change in delay value, a

settling time tEDV is required before the input is

accurately delayed.

SERIAL MODE (MD = 0)

While observing data setup (tDSC) and data hold

(tDHC) requirements, timing data is loaded in

MSB-to-LSB order by the rising edge of the clock

(SC) while the enable (AE) is high, as shown in

Figure 4. The falling edge of the enable (AE)

activates the new delay value which is reflected

at the output after a settling time tEDV. As data is

shifted into the serial data input (SI), the previous

contents of the 8-bit input register are shifted out

of the serial output port pin (SO) in MSB-to-LSB

order, thus allowing cascading of multiple

devices by connecting the serial output pin (SO)

of the preceding device to the serial data input

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