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IDT72T20118L5BB Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT72T20118L5BB
Description  2.5 VOLT HIGH-SPEED TeraSync??DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72T20118L5BB Datasheet(HTML) 1 Page - Integrated Device Technology

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DECEMBER 2003
DSC-5996/8
 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
32,768 x 20/65,536 x 10,
65,536 x 20/131,072 x 10
131,072 x 20/262,144 x 10,
262,144 x 20/524,288 x 10
IDT72T2098, IDT72T20108
IDT72T20118, IDT72T20128
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
32,768 x 20 or 65,536 x 10
65,536 x 20 or 131,072 x 10
131,072 x 20 or 262,144 x 10
262,144 x 20 or 524,288 x 10
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D0 -Dn (x20, x10)
SREN
MRS
REN
RCLK
OE
Q0 -Qn (x20, x10)
OFFSET REGISTER
PRS
FWFT
SEN
RT
5996 drw01
BUS
CONFIGURATION
OW
FSEL0
FSEL1
IW
MARK
SCLK
RCS
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TMS
TDO
TDI
TRST
RSDR
WCS
ERCLK
EREN
HSTL I/0
CONTROL
Vref
HSTL
WSDR
SI
SO
FEATURES:
••••• Choose among the following memory organizations:
IDT72T2098
32,768 x 20/65,536 x 10
IDT72T20108
65,536 x 20/131,072 x 10
IDT72T20118
131,072 x 20/262,144 x 10
IDT72T20128
262,144 x 20/524,288 x 10
Up to 250MHz Operation of Clocks
- 4ns read/write cycle time, 3.2ns access time
Users selectable input port to output port data rates, 500Mb/s
Data Rate
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
User selectable HSTL or LVTTL I/Os
Read Enable & Read Clock Echo outputs aid high speed operation
••••• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
••••• 3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write
Operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets
Dedicated serial clock input for serial programming of flag offsets
User selectable input and output port bus sizing
-x20 in to x20 out
-x20 in to x10 out
-x10 in to x20 out
-x10 in to x10 out
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty and Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using
OR and IR flags)
Output enable puts data outputs into High-Impedance state
JTAG port, provided for Boundary Scan function
208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (-40
°°°°°C to +85°°°°°C) is available
FUNCTIONAL BLOCK DIAGRAM


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