conversion. The sampling interval occurs at the end of

the acquisition interval. The ACQMOD (acquisition

mode) bit in the input control byte (Table 1) offers two

options for acquiring the signal: an internal and an

external acquisition. The conversion period lasts for 13

clock cycles in either the internal or external clock or

acquisition mode. Writing a new control byte during a

conversion cycle aborts the conversion and starts a

new acquisition interval.

Internal Acquisition

Select internal acquisition by writing the control byte

with the ACQMOD bit cleared (ACQMOD = 0). This

causes the write pulse to initiate an acquisition interval

whose duration is internally timed. Conversion starts

when this acquisition interval ends (three external

cycles or approximately 1µs in internal clock mode)

(Figure 4). Note that, when the internal acquisition is

combined with the internal clock, the aperture jitter can

be as high as 200ps. Internal clock users wishing to

achieve the 50ps jitter specification should always use

external acquisition mode.

External Acquisition

Use external acquisition mode for precise control of the

sampling aperture and/or dependent control of acquisi-

tion and conversion times. The user controls acquisition

and start-of-conversion with two separate write pulses.

The first pulse, written with ACQMOD = 1, starts an

acquisition interval of indeterminate length. The second

write pulse, written with ACQMOD = 0, terminates

acquisition and starts conversion on WR’s rising edge

(Figure 5).

The address bits for the input multiplexer must have the

same values on the first and second write pulse.

Power-down mode bits (PD0, PD1) can assume new

values on the second write pulse (see the Power-Down

Modes section). Changing other bits in the control byte

corrupts the conversion.

Reading a Conversion

A standard interrupt signal, INT, is provided to allow the

MAX1261/MAX1263 to flag the µP when the conversion

has ended and a valid result is available. INT goes low

when the conversion is complete and the output data is

ready (Figures 4 and 5). It returns high on the first read

cycle or if a new control byte is written.

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________

11

Table 1. Control Byte Functional Description

ACQMOD = 0: Internal acquisition mode

ACQMOD = 1: External acquisition mode

ACQMOD

D5

Full power-down mode. Clock mode is unaffected.

PD1 and PD0 select the various clock and power-down modes.

D7, D6

0

PD1, PD0

BIT

Normal operation mode. Internal clock mode selected.

Address bits A2, A1, A0 select which of the 8/4 (MAX1261/MAX1263) channels are to be converted

(Tables 3 and 4).

A2, A1, A0

1

Normal operation mode. External clock mode selected.

D2, D1, D0

UNI/BIP = 0: Bipolar mode

UNI/BIP = 1: Unipolar mode

1

1

0

Standby power-down mode. Clock mode is unaffected.

UNI/BIP

D3

0

1

SGL/DIF = 0: Pseudo-differential analog input mode

SGL/DIF = 1: Single-ended analog input mode

In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage

difference between two channels is measured (Tables 2 and 3).

SGL/DIF

0

D4

FUNCTION

NAME