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ADCMP582 Datasheet(PDF) 1 Page - Analog Devices |
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ADCMP582 Datasheet(HTML) 1 Page - Analog Devices |
1 / 16 page Ultrafast SiGe Voltage Comparator Preliminary Technical Data ADCMP580/ADCMP581/ADCMP582 Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. FEATURES 150 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter(DJ) 200 fs random jitter (RJ) −2 V to +3 V input range with +5 V/−5.2 V supplies On-chip terminations at both input pinsl Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB APPLICATIONS Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration GENERAL DESCRIPTION The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage comparators fabricated on Analog Devices, Inc.’s proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers; the ADCMP581 features reduced swing ECL (negative ECL) output drivers; and the ADCMP582 features reduced-swing PECL (positive ECL) output drivers. The three comparators offer 150 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs random jitter (RJ). Overdrive and slew rate dispersion is typically less than 25 ps. FUNCTIONAL BLOCK DIAGRAM VP NONINVERTING INPUT VTP TERMINATION VTN TERMINATION VN INVERTING INPUT LE INPUT HYS Q OUTPUT Q OUTPUT LE INPUT ADCMP580/ ADCMP581/ ADCMP582 CML/ECL/ PECL Figure 1. The ±5 V power supplies enable a wide −2 V to +3 V input range with logic levels referenced to the CML/NECL/PECL outputs. The three inputs have 50 Ω on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input. The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to ground. The NECL output stages are designed to directly drive 400 mV into 50 Ω terminated to −2 V. The PECL output stages are designed to directly drive 400 mV into 50 Ω terminated to VCCO − 2 V. High speed latch and programmable hysteresis are also provided. The differential latch input controls are also 50 Ω terminated to an independent VTT pin to interface to either CML or ECL or to PECL logic. The ADCMP580/ADCMP581/ADCMP582 are available in a 16-lead LFCSP package. © 2004 |
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