CY3120
Document #: 38-03049 Rev. *C
Page 2 of 8
Functional Description
Warp® is a state-of-the-art HDL compiler for designing with
Cypress’s CPLDs. Warp utilizes a subset of IEEE 1076/1164
VHDL and IEEE 1364 Verilog as its Hardware Description
Languages (HDL) for design entry. Then, it synthesizes and
optimizes the entered design, and outputs a JEDEC or Intel®
hex file for the desired PLD or CPLD (see Figure 1).
Furthermore, Warp accepts VHDL or Verilog produced by the
Active-HDL FSM graphical Finite State Machine editor. For
simulation, Warp provides a timing simulator, as well as VHDL
and Verilog timing models for use with third party simulators.
VHDL and Verilog Compilers
VHDL and Verilog are powerful, industry standard languages
for behavioral design entry and simulation, and are supported
by all major vendors of EDA tools. They allow designers to
learn a single language that is useful for all facets of the design
process.
VHDL and Verilog offer designers the ability to describe
designs at many different levels. At the highest level, designs
can be entered as a description of their behavior. This behav-
ioral description is not tied to any specific target device. As a
result, simulation can be done very early in the design to verify
correct functionality, which significantly speeds the design
process.
The Warp syntax for VHDL and Verilog includes support for
intermediate level entry modes such as state tables and
Boolean entry. At the lowest level, designs can be described
using gate-level descriptions. Warp gives the designer the
flexibility to inter-mix all of these entry modes.
In addition, Verilog and VHDL allow you to design hierarchi-
cally, building up entities in terms of other entities. This allows
you to work either “top-down” (designing the highest levels of
the system and its interfaces first, then progressing to greater
and greater detail) or “bottom-up” (designing elementary
building blocks of the system, then combining these to build
larger and larger parts) with equal ease.
Because these languages are IEEE standards, multiple
vendors offer tools for design entry and simulation at both high
and low levels and synthesis of designs to different silicon
targets. The use of device-independent behavioral design
entry gives users the freedom to easily migrate to high volume
technologies. The wide availability of VHDL and Verilog tools
provides complete vendor independence as well. Designers
can begin their project using Warp for Cypress CPLDs and
convert to high volume ASICs using the same VHDL or
Verilog
behavioral
description
with
industry-standard
synthesis tools.
The VHDL and Verilog languages also allow users to define
their own functions. User-defined functions allow users to
extend the capabilities of the language and build reusable files
of tested routines. VHDL and Verilog provide control over the
timing of events or processes. They have constructs that
identify processes as either sequential, concurrent, or a
combination of both. This is essential when describing the
interaction of complex state machines.
VHDL and Verilog are rich programming languages. Their
flexibility reflects the nature of modern digital systems and
allows designers to create accurate models of digital designs.
Because they are not verbose languages they are easy to
learn and compile. In addition, models created in VHDL and
Verilog can readily be transported to other EDA Environments.
Warp supports IEEE 1076/1164 VHDL including loops,
for/generate statements, full hierarchical designs with
packages, enumerated types, and integers as well as IEEE
1364 Verilog including loops, reduction and conditional
operators.
A VHDL Design Example
Design Entry
Warp descriptions specify:
• The behavior or structure of a design.
• The mapping of signals in a design to the pins of
a PLD/CPLD (optional).
The part of a Warp description that specifies the behavior or
structure of the design is called an entity/architecture pair.
Entity/architecture pairs, as their name implies, are divided
into two parts: an entity declaration, which declares the
design’s interface signals (i.e., defines what external signals
the design has, and what their directions and types are), and
a design architecture, which describes the design’s behavior
or structure.
The entity portion of a design file is a declaration of what a
design presents to the outside world (the interface). For each
external signal, the entity declaration specifies a signal name,
a direction and a data type. In addition, the entity declaration
specifies a name by which the entity can be referenced in a
design architecture. This section shows code segments from
five sample design files. The top portion of each example
features the entity declaration.
Behavioral Description
The architecture portion of a design file specifies the function
of the design. As shown in Figure 1, multiple design-entry
methods are supported in Warp. A behavioral description
Figure 1. Warp VHDL Design Flow
State Machine
VHDL
Programming
Timing
Simulator
VHDL, Verilog
&Third-Party
Simulation Models
UltraGenTM
Synthesis
and
Fitting
Verilog
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