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CY7C1327G-133BGXC Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1327G-133BGXC
Description  4-Mbit (256K x 18) Pipelined Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1327G-133BGXC Datasheet(HTML) 1 Page - Cypress Semiconductor

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PRELIMINARY
4-Mbit (256K x 18) Pipelined Sync SRAM
CY7C1327G
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-05519 Rev. *A
Revised October 21, 2004
Features
• Registered inputs and outputs for pipelined operation
• 256K ×18 common I/O architecture
• 3.3V core power supply
• 3.3V / 2.5V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Lead-Free 100-pin TQFP and 119 Ball BGA packages.
• “ZZ” Sleep Mode Option
Functional Description[1]
The CY7C1327G SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1327G operates from a +3.3V core power supply
while all outputs also operate with a +3.3V or a +2.5V supply.
All inputs and outputs are JEDEC-standard JESD8-5-
compatible.
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
BWB
BWA
CE1
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
2
MODE
CE2
CE3
GW
BWE
PIPELINED
ENABLE
DQs
DQPA
DQPB
OUTPUT
REGISTERS
INPUT
REGISTERS
E
DQA,DQPA
WRITE DRIVER
OUTPUT
BUFFERS
DQB,DQPB
WRITE DRIVER
A[1:0]
ZZ
SLEEP
CONTROL


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