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HDMP-1032A Datasheet(PDF) 11 Page - Agilent(Hewlett-Packard)

Part # HDMP-1032A
Description  Transmitter/Receiver Chip Set
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Manufacturer  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HDMP-1032A Datasheet(HTML) 11 Page - Agilent(Hewlett-Packard)

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11
Figure 6. HDMP-1034A (Rx) Timing Diagram.
HDMP-1034A (Rx) Timing Characteristics
Tc = –20
°C to +85°C, VCC = 3.15V to 3.45V. Typical values are at Tc = 25°C, VCC = 3.3V
Symbol
Parameter
Unit
Min.
Typ.
Max.
td
Synchronous Output Delay referenced to the falling
nsec
0
2.0
3.5
edge of RXCLK1, PASS System Disabled (PASSENB=0).
tdp
Synchronous Output Delay referenced to the rising
nsec
6.0
6.6
8.0
edge of REFCLK, PASS System Enabled (PASSENB=1).
tsk
Allowable skew between HSIN and REFCLK before
nsec
20% word
PASS system resets, PASSENB=1.
period
-0.4 nsec
HDMP-1034A (Rx) Timing
The Rx timing diagram when
RXREADY=1 is shown in Figure
6. The serial data stream is
deserialized into a parallel word
at 1/20 the serial baud rate.
When the PASS system is dis-
abled (PASSENB=0), there is a
latency delay of two words from
the input of the first serial bit of a
word to the parallel outputs. The
parallel outputs, RX[0-15],
RXFLAG, RXREADY, RXERROR,
RXDATA, RXCNTL and RXDSLIP
are clocked out with the falling
edge of RXCLK1 and appear after
a delay of td. RXCLK1 and its
complement RXCLK0 are both
50% duty cycle clocks.
When the PASS system is enabled
(PASSENB=1), the timing of the
parallel word is adjusted auto-
matically
± 30% of the word pe-
riod so that it can be clocked out
with the rising edge of REFCLK
and appear after a delay of tdp.
C
WORD 1
W
C
WORD 2
W
C
WORD 3
W
C
WORD 4
W
HSIN
RXCLK1
RXCLK0
REFCLK
tdp
td
RX[0]
BIT 0
NOTE: W = 16 BIT WORD FIELD,
C = 4 BIT CODE FIELD


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