HDMP-1032A datasheet(7/32 Pages) HP

Part #	HDMP-1032A

Description	Transmitter/Receiver Chip Set

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Manufacturer	HP [Agilent(Hewlett-Packard)]

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When the Tx and Rx clock are

not synchronous, FIFO’s are usu-

ally used to cross the frequency

domains. The size of the FIFO

and the frequency difference

determine the maximum packet

size of transmission.

When the clock from the Tx is

synchronous with the Rx clock,

data can be transmitted continu-

ously without FIFO’s since the

parallel output data is synchro-

nous with the local REFCLK.

However, due to link distance and

other physical variables, the rela-

tive phase of the REFCLK to the

recovered data is unpredictable.

Because of this unknown phase,

the sampling of the recovered

word must be adjusted so that the

internal setup/hold times are not

violated. Furthermore, in a multi-

channel system, the setting of the

phase must be consistent so that

time slots across the channels

are preserved.

The PASS system was designed to

address these issues by sensing

the phase difference between the

local REFCLK with the recovered

clock, and shifts the phase of

the parallel output data with the

DELAY block, such that it can be

clocked out with the rising edge

static valid code-field bits being

embedded within the data-field.

Enhanced simplex mode can be

turned off (ESMPXENB=0) to

make it compatible with

previous versions of G-Link.

With this mode turned off and

TXFLGENB=1, the flag bit is

sent unscrambled to the Rx.

If TXFLGENB=0, the flag

bit will alternate at the Tx.

When RXFLGENB=0, the Rx

will use this alternating flag for

error checking.

Parallel Automatic Synchronization

System (Pass)

As shown in Figure 4, this system

consists of three blocks: the

parallel delay block (DELAY),

the output latch block (OUTPUT

LATCH), and the synchronization

logic block (SYNC LOGIC). This

system was designed to provide

a simple interface to the parallel

outputs for a synchronous system.

Background

Traditionally, the parallel outputs

are clocked out with the falling

edge of RXCLK1 as shown in

Figure 4.1. Since this clock is

recovered from the serial data,

this clock is synchronous with

the remote clock at the Tx.

Demultiplexer (DEMUX)

This block takes the recovered

serial data from the CDR block

and demultiplexes it into a 20-bit

parallel word comprised of a

16-bit word-field and 4-bit

code-field.

Decoder (DECODE)

This block decodes the 4-bit

code-field and determines

whether the 16-bit word-field is:

normal or inverted; data, control,

or idle words; or errors. The

flag bit is also decoded from

the data word.

Word Alignment (WORD ALIGN)

This block detects the error out-

put of the decoder block. Upon

detecting two consecutive errors,

WORD ALIGN requests a bit

adjustment to the clock generator

(assuming WSYNCDSB=0).

If enhanced simplex mode is

engaged (ESMPXENB=1), the

Word Align block looks for a

transition in the scrambled flag

bit over a window of 32 words.

If a transition is not detected,

WORD ALIGN requests a bit

adjustment to the clock generator

(assuming WSYNCDSB=0).

When the bit adjustment output

has been low for 64 up to 128

words, the RXREADY output goes

high. If the bit adjustment output

goes high, RXREADY

immediately goes low.

Flag Descrambler

(FLAG DESCRM)

This block descrambles the flag

bit if the enhanced simplex mode

is engaged (ESMPXENB=1); oth-

erwise, the flag bit is unaltered.

Scrambling ensures that the flag

bit is dynamic and thus can be

detected by the word alignment

block. Scrambling of the flag

bit provides an extra level of

protection to guard against im-

proper word alignment caused by

Figure 4.1. Traditional G-Link configuration with PASS disabled (PASSENB=0).

Recovered data words and RXCLK0/1 are synchronous with TXCLK.

HSOUT±

HSIN±

Rx

Tx

TXCLK

REFCLK

SRQOUT

NC

SRQIN

SHFIN

SHFOUT

RXCLK0/1

RX[0-15]

NC

DATA 16 BITS

TX[0-15]

PASSENB

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