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WCMA4008C1X
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Switching Waveforms
Read Cycle No.1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
8.
Full Device operatin requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at Vcc(min) > 100 µs.
9.
Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT