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LM5035 Datasheet(PDF) 16 Page - National Semiconductor (TI) |
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LM5035 Datasheet(HTML) 16 Page - National Semiconductor (TI) |
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16 / 28 page  Gate Driver Outputs (HO & LO) (Continued) Synchronous Rectifier Control Outputs (SR1 & SR2) Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low output voltage converters. The reduction of rectifier forward voltage drop (0.5V - 1.5V) to 10mV - 200mV V DS voltage for a MOSFET significantly reduces rectification losses. In a typical applica- tion, the transformer secondary winding is center tapped, with the output power inductor in series with the center tap. The SR MOSFETs provide the ground path for the energized secondary winding and the inductor current. Figure 5 shows that the SR2 MOSFET is conducting while HO enables power transfer from the primary. The SR1 MOSFET must be disabled during this period since the secondary winding connected to the SR1 MOSFET drain is twice the voltage of the center tap. At the conclusion of the HO pulse, the induc- tor current continues to flow through the SR1 MOSFET body diode. Since the body diode causes more loss than the SR MOSFET, efficiency can be improved by minimizing the T2 period while maintaining sufficient timing margin over all conditions (component tolerances, etc.) to prevent shoot- through current. When LO enables power transfer from the primary, the SR1 MOSFET is enabled and the SR2 MOSFET is off. During the time that neither HO nor LO is active, the inductor current is shared between both the SR1 and SR2 MOSFETs which effectively shorts the transformer secondary and can- cels the inductance in the windings. The SR2 MOSFET is disabled before LO delivers power to the secondary to pre- vent power being shunted to ground. The SR2 MOSFET body diode continues to carry about half the inductor current until the primary power raises the SR2 MOSFET drain volt- age and reverse biases the body diode. Ideally, dead-time T1 would be set to the minimum time that allows the SR MOSFET to turn off before the SR MOSFET body diode starts conducting. The SR1 and SR2 outputs are powered directly by the VCC regulator. Each output is capable of sourcing and sinking 0.5A peak. Typically, the SR1 and SR2 signals control SR MOSFET gate drivers through a pulse transformer. The ac- tual gate sourcing and sinking currents are provided by the secondary-side bias supply and gate drivers. The timing of SR1 and SR2 with respect to HO and LO is shown in Figure 5. SR1 is configured out of phase with HO and SR2 is configured out of phase with LO. The deadtime between transitions is programmable by a resistor con- nected from the DLY pin to the AGND pin. Typically, R DLY is set in the range of 10k Ω to 100kΩ. The deadtime periods can be calculated using the following formulae: T1=[R DLY x 2.8ps] + 20ns T2=[R DLY x 1.35ps] + 6ns To set the minimum (propagation delays only) deadtime, the DLY pin should be left open or connected to the REF pin. Any resistor value above 300k Ω connected between the DLY pin and AGND will also provide the minimum period (ap- proximately 5 ns). Thermal Protection Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated junction temperature is exceeded. When activated, typically at 165˚C, the controller is forced into a low power standby state with the output drivers (HO, LO, SR1 and SR2), the bias regulators (VCC and REF) disabled. This helps to prevent catastrophic failures from accidental device overheating. During thermal shutdown, the soft-start capacitor is fully discharged and the controller follows a normal start-up se- quence after the junction temperature falls to the operating level (145˚C). 20177521 FIGURE 5. HO, LO, SR1 and SR2 Timing Diagram www.national.com 16 |
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