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ML9261AMB Datasheet(PDF) 8 Page - OKI electronic componets |
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ML9261AMB Datasheet(HTML) 8 Page - OKI electronic componets |
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8 / 16 page  FEDL9261A-01 OKI Semiconductor ML9261A 8/16 AC Characteristics-1 (VDD = 4.5 to 5.5 V, VDISP = 20 to 60 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Max. Unit CLK Pulse Width tW (CLK) — 80 150 ns DIN Setup Time tSU (D-CLK) — 50 — ns DIN Hold Time tH (CLK-D) — 50 — ns CLK-LS Setup Time tSU (CLK-LS) — 50 — ns tSU (LS-CLK) During normal operation 50 — ns LS-CLK Setup Time tSU (L-CLK) At display data reset 50 — ns CLK-LS Hold Time tH (CLK-L) At display data reset 50 — ns LS-CHG Setup Time tSU (LS-CHG) — 50 — ns LS- CL Setup Time tSU (LS-CL) — 50 — ns LS Pulse Width tW (LS) — 80 — ns CHG Pulse Width tW (CHG) — 10 — µs CL Pulse Width tW (CL) — 10 — µs DOUT Delay time tPD, tPRD Load: 30 pF — 50 ns tDLH — 2.0 µs tDHL — 2.0 µs Driver Output Delay Time tDRHL VDISP = 40 V Load: 1.0 k Ω resistance in parallel with 20 pF capacitance — 2.0 µs tTLH — 5.0 µs Driver Output Slew Rate tTHL VDISP = 40 V Load: 1.0 k Ω resistance in parallel with 20 pF capacitance — 5.0 µs AC Characteristics-2 (VDD = 3.0 to 3.6 V, VDISP = 20 to 60 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Max. Unit CLK Pulse Width tW (CLK) — 80 150 ns DIN Setup Time tSU (D-CLK) — 50 — ns DIN Hold Time tH (CLK-D) — 50 — ns CLK-LS Setup Time tSU (CLK-LS) — 50 — ns tSU (LS-CLK) During normal operation 50 — ns LS-CLK Setup Time tSU (L-CLK) At display data reset 50 — ns CLK-LS Hold Time tH (CLK-L) At display data reset 50 — ns LS-CHG Setup Time tSU (LS-CHG) — 50 — ns LS- CL Setup Time tSU (LS-CL) — 50 — ns LS Pulse Width tW (LS) — 80 — ns CHG Pulse Width tW (CHG) — 10 — µs CL Pulse Width tW (CL) — 10 — µs DOUT Delay time tPD, tPRD Load: 30 pF — 50 ns tDLH — 3.0 µs tDHL — 3.0 µs Driver Output Delay Time tDRHL VDISP = 40 V Load: 1.0 k Ω resistance in parallel with 20 pF capacitance — 3.0 µs tTLH — 5.0 µs Driver Output Slew Rate tTHL VDISP = 40 V Load: 1.0 k Ω resistance in parallel with 20 pF capacitance — 5.0 µs |
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