FEDS5424331-01

1Semiconductor

MSM5424331

2/34

FEATURES

• Switching between FIFO and Block Access modes by the D/F pin

FIFO mode:

Serial write/read operation by line-by-line accessing

Block Access mode: Fast write/read operation on an 8-word basis by the

RAS and CAS control

• Organization of 768 × 290 × 24 bits

FIFO mode:

Input

× 12 or × 24 controlled by L/UWE

Output

× 24

Block Access mode:

Input

× 12 (Two 768 × 290 × 12-bit banks are controlled by L/UWE.)

Output

× 12 (Two 768 × 290 × 12-bit banks are controlled by A9.)

• Asynchronous operation

Input and output asynchronous operation enabled only in the FIFO mode Single write or read operation in the

Block Access mode

• Serial Read and Write Cycle times (in both the FIFO mode and the Block Access mode)

Cycle time:

60 ns

Access time: 50 ns

• Operating supply voltage: 2.8 to 3.3 V

• Refresh

FIFO mode:

Self refresh

Block Access mode: by the

CAS before RAS refresh function (290 cycles/8 ms)

• Address input

FIFO mode:

Setting random line address by the serial address input

Block Access mode: Setting random address in the address multiplexer by the

RAS and CAS control

• Selectable serial address input setting or various address resetting in the FIFO mode

• Package:

70-pin 400 mil plastic TSOP (Type 2) (TSOP(2)70-P-400-0.50-K) (Product: MSM5424331TS-AK)