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ML7051LA Datasheet(PDF) 5 Page - OKI electronic componets |
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ML7051LA Datasheet(HTML) 5 Page - OKI electronic componets |
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5 / 24 page  FEDL7051LA-02 1Semiconductor ML7051LA 5/24 CLK and Configuration Pin Name I/O Internal Pull Up/Down Initial Value Pin Placement Description SCLK12 I — — E12 Master clock (12 MHz) input pin (Power level: CMOS level) XCLK I — — E13 User clock input pin SCLKSEL I Pull down — A11 System clock select pin L: Select CLK divided by internal PLL H: Select XCLK input signal RESETn I — — C13 Hardware reset pin (Reset = L) BBWSEL I — — C10 BANK0 region bit width select pin L: 8-bit H: 16-bit REMAP0 I — — A12 REMAP1 I B13 REMAP select pin during boot up REMAP[1:0] = “00” Reserved “01” Stacked Flash ROM “10” External MCS[1] device “11” External MCS[0] device Memory I/F Pin Name I/O Internal Pull Up/Down Initial Value Pin Placement Description MA[19:0] O — L [*1] External address bus MD[15:0] I/O — Z [*2] External data bus MWEn O — H N10 External write enable signal output MREn O — H M11 External read enable signal output MCSn0 O — H K10 External RAM space chip select MCSn1 O — H N11 External I/O space chip select MBSn0 O — H N12 External lower byte select MBSn1 O — H M12 External upper byte select MOEn0 O — H K11 External MCS[0] device output enable (MCSn0 and WREn OR output) MOEn1 O — H L11 External MCS[1] device output enable (MCSn1 and WREn OR output) MWAIT I — — F3 External wait signal input (Pin shared with GPIO1) [*1] MA19: H3; MA18: H4; MA17: H2; MA16: J2; MA15: H1; MA14: J4 MA13: K2; MA12: J1; MA11: J3; MA10: K1; MA9: L2; MA8: K4; MA7: M2 MA6: M1; MA5: N2; MA4: L3; MA3: N3; MA2: L4; MA1: M3; MA0: L5 [*2] MD15: N5; MD14: K5; MD13: M5; MD12: N6; MD11: M6; MD10: M7 MD9: K7; MD8: N7; MD7: L8; MD6: K8; MD5: M8; MD4: M9; MD3: N8; MD2: K9; MD1: M10; MD0: L10 |
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