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AN77L12M Datasheet(PDF) 3 Page - Panasonic Semiconductor

Part # AN77L12M
Description  3-pin Low Power Loss Voltage Regulato (100mA Type)
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Manufacturer  PANASONIC [Panasonic Semiconductor]
Direct Link  http://www.panasonic.com/industrial/
Logo PANASONIC - Panasonic Semiconductor

AN77L12M Datasheet(HTML) 3 Page - Panasonic Semiconductor

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3
Voltage Regulators
AN77L00/AN77L00M Series
Output voltage
Input stability
Load stability
Bias current under no load
Bias current fluctuation under load
Bias current before regulation start
Ripple rejection ratio
Min. input/output voltage difference (1)
Min. input/output voltage difference (2)
Output noise voltage
Output voltage temperature coefficient
VO
REGIN
REGL
Ibias
∆I
bias
Irush
RR
VDIF (min) 1
VDIF (min) 2
Vno
∆V
O/Ta
Tj=25˚C
VI=3.62 to 13.62V, Tj=25˚C
IO=0 to 100mA, Tj=25˚C
IO=0mA, Tj=25˚C
IO=0 to 100mA, Tj=25˚C
VI=2.7V, IO=0mA, Tj=25˚C
VI=3.62 to 5.62V, f=120Hz
VI=2.7V, IO=50mA, Tj=25˚C
VI=2.7V, IO=100mA, Tj=25˚C
f=10Hz to 100kHz
Tj= –30 to+125˚C
2.88
60
3
2
8
0.9
3
1.5
70
0.12
0.22
70
0.2
3.12
60
60
1.5
5
5
0.25
0.3
V
mV
mV
mA
mA
mA
dB
V
V
µV
mV/˚C
Parameter
Symbol
Condition
min
typ
max
Unit
s Electrical Characteristics (Ta=25˚C)
• AN77L03/M (3V, 100mA Type)
Note 1) Under Tj=25˚C, each test duration can be set short (within 10ms) and the characteristic drift with temperature rise at
joints of the chip may be ignored.
Note 2) VI=4V, IO=50mA, CO=10
µF unless otherwise specified.
Output voltage
Input stability
Load stability
Bias current under no load
Bias current fluctuation under load
Bias current before regulation start
Ripple rejection ratio
Min. input/output voltage difference (1)
Min. input/output voltage difference (2)
Output noise voltage
Output voltage temperature coefficient
Tj=25˚C
VI= 4.14 to 14.14V, Tj=25˚C
IO= 0 to 100mA, Tj= 25˚C
IO= 0mA, Tj= 25˚C
IO= 0 to 100mA, Tj= 25˚C
VI= 3.15V, IO= 0mA, Tj=25˚C
VI= 4.14 to 6.14V, f=120Hz
VI= 3.15V, IO= 50mA, Tj= 25˚C
VI= 3.15V, IO=100mA, Tj= 25˚C
f=10Hz to 100kHz
Tj= –30 to+125˚C
3.36
59
3.5
3
9
0.9
3
1.5
69
0.12
0.22
75
0.23
3.64
60
60
1.5
5
5
0.25
0.41
Parameter
Symbol
Condition
min
typ
max
Unit
• AN77L035/M (3.5V, 100mA Type)
Note 1) Under Tj=25˚C, each test duration can be set short (within 10ms) and the characteristic drift with temperature rise at
joints of the chip may be ignored.
Note 2) VI=4.5V, IO=50mA, CO=10
µF unless otherwise specified.
VO
REGIN
REGL
Ibias
∆I
bias
Irush
RR
VDIF (min) 1
VDIF (min) 2
Vno
∆V
O/Ta
V
mV
mV
mA
mA
mA
dB
V
V
µV
mV/˚C
Output voltage
Input stability
Load stability
Bias current under no load
Bias current fluctuation under load
Bias current before regulation start
Ripple rejection ratio
Min. input/output voltage difference (1)
Min. input/output voltage difference (2)
Output noise voltage
Output voltage temperature coefficient
Tj=25˚C
VI= 4.66 to 14.66V, Tj= 25˚C
IO= 0 to 100mA, Tj= 25˚C
IO= 0mA, Tj= 25˚C
IO= 0 to 100mA, Tj=25˚C
VI=3.6V, IO= 0mA, Tj= 25˚C
VI= 4.66 to 6.66V, f=120Hz
VI=3.6V, IO=50mA, Tj= 25˚C
VI=3.6V, IO=100mA, Tj= 25˚C
f=10Hz to 100kHz
Tj= –30 to+125˚C
3.84
59
4
3
9
0.9
3
1.5
69
0.12
0.23
80
0.26
4.16
60
60
1.5
5
5
0.25
0.3
Parameter
Symbol
Condition
min
typ
max
Unit
• AN77L04/M (4V, 100mA Type)
Note 1) Under Tj=25˚C, each test duration can be set short (within 10ms) and the characteristic drift with temperature rise at
joints of the chip may be ignored.
Note 2) VI=5V, IO=50mA, CO=10
µF unless otherwise specified.
VO
REGIN
REGL
Ibias
∆I
bias
Irush
RR
VDIF (min) 1
VDIF (min) 2
Vno
∆V
O/Ta
V
mV
mV
mA
mA
mA
dB
V
V
µV
mV/˚C


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