FEDL9225B-03

1Semiconductor

MSM9225B

10/16

TIMING DIAGRAMS

Separate Bus Mode

Read access timing

t

cyc

t

RAH

t

WRDH

t

RDH

t

ARLDLY

t

WRDYL

t

RDLY

t

RS

t

HRC

CS

A7-0

AD7-0/

D7-0

PRD/SRW

PRDY/SWAIT

t

ARDDLY

Note:

The

PRDY signal may be output depending on the internal state of the MSM9225B.

Write access timing

t

cyc

t

WAH

t

WRH

t

WDS

t

ARLDLY

t

WRDYL

t

WRL

t

WS

t

HWC

CS

A7-0

AD7-0/

D7-0

PWR

PRDY/SWAIT

t

WDH

t

ARWDLY

Note:

The

PRDY signal may be output depending on the internal state of the MSM9225B.