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MIC9130 Datasheet(PDF) 11 Page - Micrel Semiconductor |
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MIC9130 Datasheet(HTML) 11 Page - Micrel Semiconductor |
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11 / 19 page  April 2005 11 M9999-040805 MIC9130 Micrel, Inc. VCC Undervoltage Lockout The VCC voltage is internally divided down and compared to a 1.21V internal bandgap reference. As VCC rises above the turn-on threshold, it disables the Vcc undervoltage lockout circuit.Onceabovetheturn-onthreshold,hysteresisprevents the lockout circuit from disabling the IC until the VCC voltage falls below the lower threshold. Line Undervoltage Circuit (UVLO) The line voltage is monitored by an external resistor divider and fed into the negative input of the line UVLO comparator. As the comparator trip point is exceeded, the line UVLO circuit is disabled. Hysteresis built into the comparator prevents the circuit from toggling on an off in the presence of noise or a high input line impedance. The line voltage turn-on trip point is: V V R2 R1 R2 LINE_ON THRESHOLD = × + where: VTHRESHOLD is the voltage level of the internal comparator reference, typically 1.21V. The line hysteresis is equal to: V V R1 R2 R2 HYSTERESIS HYST = × + where: VHYST is the internal hysteresis level, typically 75mV. VHYSTERESIS is the hysteresis of the line input voltage The MIC9130 will be disabled when the line voltage drops back down to: V V V V V R2 R1 R2 LINE_OFF LINE_ON HYTERESIS THRESHOLD HYST = − = − ( )× + Enable A low level on the enable pin turns off all the functions of the MIC9130 and places it in a low quiescent current state. The output driver is in a low state. When the enable pin is pulled high, the MIC9130 goes through its normal start up sequence including undervoltage lock out and soft start. When not used, the pin should be connected to VCC. Oscillator Block An external resistor and capacitor set the oscillator frequency. The MIC9130 contains an internal divide-by-two circuit that limits the maximum duty cycle at the gate drive to 50%. The oscillator frequency for the MIC9130 is twice the output switching frequency. Oscillator Pin The operation of the oscillator is shown in Figure 5. The volt- age waveform at the OSC pin is a sawtooth whose amplitude increases as capacitor Cosc is charged up through ROSCfrom the 5V bias. When the OSC pin voltage reaches the internal comparator upper threshold, COSC is quickly discharged to zero volts by an internal MOSFET. After a brief delay, typi- cally 75ns, the internal MOSFET is turned off and the COSC charges, repeating the cycle. Figure 5 show the relationship between the oscillator and gate drive waveforms. The delays in the IC force the duty cycle of the gate drive signal to be slightly less than 50% duty cycle (typically 48%). For VBIAS = 5V and a peak oscillator waveform voltage of 3V, the design equations simplify to: Charging tCHARGE t t R C = × × 0 92 . Discharging t C DISCHARGE t ≈ × 40 MIC9130 S SET RESET R Q /Q LINE UVLO VCC UVLO VCC AGND VIN UVLO UVLO R1 1.21V R2 2 11 13 PGND 15 OUT 16 SS 4µA 5V 12 Figure 4: UVLO and Soft Start Circuits |
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