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IND16305 Datasheet(PDF) 2 Page - Integral Corp. |
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IND16305 Datasheet(HTML) 2 Page - Integral Corp. |
2 / 7 page IND16305 Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by 2 PIN CONFIGURATION (Top View) • Ensure that the VDD1, VDD2, VSS1 and VSS2 pins are all used, and that VSS1 and VSS2 are used at the same potential (connect at same point near IC). • Pin 33 is connected to the lead frame, and must therefore be left open. DESCRIPTION OF PINS Pin Symbol Pin Name Pin No. Description BLK Output blank input 37 See truth table A RIGHT data input/output 30 Serial data input/output* When R/L = H A: Input B:Output B LEFT data input/output 35 When R/L = L A: Output B: Input CLK Clock input 31 Shift executed on rise STB Latch enable input 36 H: Latch, L: Data-through R/L Shift direction control input 25 H: Right shift modeA →O1 ···O40→B L : Left shift mode B →O40→···O1 A CLR Clear input 32 L: Shift register ALL L PC Polarity reversal input 27 See truth table O1 to O40 High withstand voltage outputs 1 to 20 45 to 64 200 V, 400 mA max. VDD1 Logic block power supply 26, 39 5 V ± 10 % VDD2 Driver block power supply 21, 44 30 V to 180 V VSS1 Logic block ground 24, 41 Connect to system GND VSS2 Driver block ground 22, 23, 42, 43 Connect to system GND at same point. NC Unused pins 28, 29, 33, Non-connection 34, 38, 40 Ensure that pin 33 is left open. * Data resulting from inversion of the data input is input to the shift register, and data resulting from inversion of the shift register data is output to the output. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 3 4 5 6 7 8 9 10 11 13 14 15 16 17 19 20 21 22 23 24 12 VDD2 VSS2 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 VSS2 VSS1 O1 O2 O3 O4 O5 50 49 48 47 46 45 44 43 42 41 VDD2 VSS2 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 VSS2 VSS1 O40 O38 O37 O36 |
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