FEDS51V4221C-03

1Semiconductor

MSM51V4221C

5/16

OPERATION

Write Operation

The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by

cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.

Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e. SWCK cycles

while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data

registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle.

Write Reset: RSTW

The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW

setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely

controlled by the SWCK rising edge after the high level of RSTW, the states of WE are ignored in the write reset

cycle.

Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK

cycles.

Data Inputs: D

Write Clock: SWCK

The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.

Data-in setup time t

Write Enable: WE

WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the

input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)

restrictions, because the MSM51V4221C is in fully static operation as long as the power is on. Note that WE setup

and hold times are referenced to the rising edge of SWCK.