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IDT72V3692L10PF Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72V3692L10PF Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 29 page  7 COMMERCIALTEMPERATURERANGE IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM 16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3682/72V3692/72V36102 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x ICC(f) + Σ(CL x VCC2 X fo) N where: N = number of outputs = 36 CL = output capacitance load fo = switching frequency of an output Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) 0 10 20 3040 506070 0 10 20 30 40 50 60 fS Clock Frequency MHz fdata = 1/2 fS TA = 25 °C CL = 0 pF 4679 drw 04 70 90 80 100 80 90 100 VCC = 3.3V VCC = 3.6V VCC = 3.0V |
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