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Z90251 Datasheet(PDF) 11 Page - Zilog, Inc. |
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Z90251 Datasheet(HTML) 11 Page - Zilog, Inc. |
11 / 97 page Z90255 ROM and Z90251 OTP 32 KB Television Controller with OSD PS001301-0800 3 Figure 2 Z90255 Block Diagram PWM 6 can be either a 6-bit or 14-bit output. The Z90255 takes full advantage of ZilogÕs Z8 expanded register file space to offer greater flexibility in creating a user-friendly On-Screen Display (OSD). Three basic addressing spaces are available: Program memory, Video RAM (VRAM) and the Register file. The register file is composed of 300 bytes of general-purpose registers, 16 control and status registers, one I/O port register and three reserved registers. RESET Oscillator WDT Counter Timer Counter Timer 4-Bit ADC IR Counter Port 6 300 Byte Register File Port 2 18 KB by 7-Bit Character PWM 11 & 6 PWM 1 to PWM 10 (14-bit) (6-bit) XTAL1 XTAL2 RESET ADC0 ADC1 ADC2 ADC3 IRIN P60 P61 P62 P63 P21 P22 P23 P24 P25 P26 P27 P20 PWM11 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM8 PWM9 PWM10 SCLK0 SDATA0 I 2 C P50 P51 P52 P53 P54 P55 P56 Port 5 Interface SCLK1 SDATA1 ROM or OTP PWM7 240 x 12-Bit Character RAM & 10 x 8-Bit 32 KB Program ROM Microprocessor Core or 32 KB Program OTP Internal On-Screen Display OSDX1 OSDX2 HSYNC VSYNC R G B VBLANK HLFTN Port 4 P40 P41 P42 P43 P44 P45 P46 P47 PWM6 Note: |
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