Z90255 ROM and Z90251 OTP

32 KB Television Controller with OSD

PS001301-0800

vi

37

Master I2C Data Register 0Ah: Bank C (I2C_DATA) ............................... 55

38

Master I

39

Port configuration Register 00h: Bank F (PCON) ..................................... 57

40

Port 2 Mode Register F6h: P2M ............................................................... 58

41

Port 2 Data Register 02h: P2 .................................................................... 58

42

Port 4 Pin-Out Selection Register 08h: Bank C (PIN_SLT) ...................... 59

43

Port 4 Data Register 05h: Bank C (PRT4_DTA)....................................... 60

44

Port 4 Direction Control Register 06h: Bank C (PRT4_DRT) ................... 61

45

PWM Mode Register 0Dh: Bank B (P_MODE) ......................................... 62

46

Port 5 Data Register 0Ch: Bank B (PRT5_DTA) ...................................... 62

47

Port 5 Direction Control Register 0Eh: Bank B (PRT5_DRT) ................... 63

48

Port 6 Data Register 03h: Bank F (PRT6_DTA) ........................................ 63

49

Port 6 Direction Control Register 02h: Bank F (PRT6_DRT) .................... 64

50

Timer Control Register 0 01h: Bank C (TCR0) ......................................... 65

51

Timer Control Register 1 02h: Bank C (TCR1) ......................................... 66

52

IR Capture Register 0 03h: Bank C (IR_CP0) .......................................... 67

53

IR Capture Register 1 04h: Bank C (IR_CP1) .......................................... 68

54

PWM Mode Register 0Dh: Bank B (P_MODE)......................................... 68

55

Port 4 Pin-Out Selection Register 08h: Bank C (PIN_SLT) ...................... 69

56

PWM 1 Data Register 02h: Bank B (PWM1) ............................................ 73

57

PWM 2 Data Register 03h: Bank B (PWM2) ............................................ 73

58

PWM 3 Data Register 04h: Bank B (PWM3) ............................................ 73

59

PWM 4 Data Register 05h:Bank B (PWM4) ............................................. 74

60

PWM 5 Data Register 06h: Bank B (PWM5) ............................................ 74

61

PWM 6 (6-bit)Data Register 07h: Bank B (PWM6)................................... 75

62

PWM 7 Data Register 08h: Bank B (PWM7) ............................................ 75

63

PWM 8 Data Register 09h: Bank B (PWM8) ............................................ 75

64

PWM 9 Data Register 0Ah: Bank B (PWM9) ............................................ 76

65

PWM 10 Data Register 0Bh: Bank B (PWM10)........................................ 76

66

PWM 6 (14-bit) High Data Register 08h: Bank F (PWM6H) ..................... 77

67

PWM 6 (14-bit) Low Data Register 09h: Bank F (PWM6L) ...................... 77

68

PWM 11 High Data Register 00h: Bank B (PWM11H) ............................. 77

69

PWM 11 Low Data Register 01h: Bank B (PWM11L) ............................... 78

70

3-Bit ADC Data Register 00h: Bank C (3ADC_DTA)................................ 81

71

4-Bit ADC Data Register 01h: Bank F (4ADC_DTA) ................................ 81

72

Operational Limits ..................................................................................... 83

73

DC Characteristics.................................................................................... 84

74

AC Characteristics .................................................................................... 85

75

Package Dimensions ................................................................................ 87