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83503 Datasheet(PDF) 5 Page - Peregrine Semiconductor Corp.

Part # 83503
Description  3.5 GHz Low Power CMOS Divide-by-8 Prescaler
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Manufacturer  PEREGRINE [Peregrine Semiconductor Corp.]
Direct Link  http://www.peregrine-semi.com
Logo PEREGRINE - Peregrine Semiconductor Corp.

83503 Datasheet(HTML) 5 Page - Peregrine Semiconductor Corp.

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PE83503
Product Specification
PEREGRINE SEMICONDUCTOR CORP.
| http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 5 of 7
VDD
IN
DEC
GND
GND
OUT
NC
GND
1000 pF
J2-7
J3
J4
J5
10 pF
C1
J1
10 pF
10 nF
C2
Figure 10. Evaluation Board Schematic Diagram
Figure 11. Evaluation Board Layout
Evaluation Kit Operation
The MSOP Prescaler Evaluation Board was
designed to help customers evaluate the PE83503
Divide-by-8 Prescaler. On this board, the device
input (pin 2) is connected to connector J1 through a
50 Ω transmission line. A series capacitor (C3)
provides the necessary DC block for the device
input. It is important to note that the value of this
capacitance will impact the performance of the
device. A value of 15pF was found to be optimal for
this board layout; other applications may require a
different value.
The device output (pin 7) is connected to connector
J3 through a 50 Ω transmission line. A series
capacitor (C1) provides the necessary DC block for
the device output. Note that this capacitor must be
chosen to have a low impedance at the desired
output frequency the device. The value of 100pF
was chosen to provide a wide operating range for
the evaluation board.
The board is constructed of a two-layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide above
ground plane model with trace width of 0.030”, trace
gaps of 0.007”, dielectric thickness of 0.028”, metal
thickness of 0.0014” and εr of 4.4. Note that the
predominate mode for these transmission lines is
coplanar waveguide.
J2 provides DC power to the device. Starting from
the lower left pin, the second pin to the right (J2-3)
is connected to the device VDD pin (1). Two
decoupling capacitors (10 pF, 1000 pF) are
included on this trace. It is the responsibility of the
customer to determine proper supply decoupling for
their design application.
The DEC pin (3) must be connected to a low
impedance AC ground for proper device operation.
On the board, two decoupling capacitors (C6 = 10
nF, C4 = 10 pF), located on the back of the board,
perform this function.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 455-0660
and ask for applications support. You may also
contact us by fax or e-mail:
Fax: (858) 455-0770
E-Mail: help@peregrine-semi.com
C3
C1


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