Product Specification

PE9701

Page 11 of 13

Document No. 70-0035-02

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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.

pin CP. The current pulses from pin CP are low

pass filtered externally and then connected to the

VCO tune voltage. PD_U pulses result in a

current source, which increases the VCO

frequency; PD_D pulses result in a current sink,

which decreases VCO frequency.

A lock detect output, LD is also provided, via the

pin Cext. Cext is the logical “NAND” of PD_U and

PD_D waveforms, which is driven through a series

2k

Ω resistor. Connecting Cext to an external

shunt capacitor provides integration. Cext also

drives the input of an internal inverting comparator

with an open drain output. Thus LD is an “AND”

function of PD_U and PD_D. See Figure 4 for a

schematic of this circuit.

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 9. Enhancement Register Bit Functionality

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

and PD_D. If the divided VCO leads the divided

PD_D pulses “high”. If the divided reference leads

is directly proportional to phase offset between the

The signals from the phase detector couple

directly to a charge pump. PD_U controls a

current source at pin CP with constant amplitude

and pulse duration approximately the same as

PD_U. PD_D similarly drives a current sink at

Bit Function

Description

Bit 0

Reserved**

Bit 1

Reserved**

Bit 2

Reserved**

Bit 3

Power down

Power down of all functions except programming interface.

Bit 4

Counter load

Immediate and continuous load of counter programming as directed by the

Bmode and

Smode inputs.

Bit 5

MSEL output

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Bit 6

Prescaler output

Drives the raw internal prescaler output (fmain) onto the Dout output.

Bit 7