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TC90A80N Datasheet(PDF) 4 Page - Toshiba Semiconductor |
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TC90A80N Datasheet(HTML) 4 Page - Toshiba Semiconductor |
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4 / 23 page  TC90A80N/F 2002-12-04 4 Pin No. Pin Name Function DC Level (V) Interface Circuit 9 YCIN Composite video signal input pin (I 2C Bus function: YCS) Because sync tip clamp is internally used, the signal should be applied after cutting the DC component using a capacitor of around 0.47 µF. Sync Tip YCS Mode : 1.86 NR Mode : 1.83 10 VSS3 Logic and DRAM GND pin (digital) Separate digital VSS from analog VSS. 0.0 ― 11 KIPVIN Killer control and pseudo vertical pulse (PV) input pin (M or H polarity can be selected using I 2C Bus.) In Killer mode, Y/C separation, vertical enhancer, CNR, and YNR are halted. PV input: Vertical mask signal for detecting skew. Apply PV which is synchronous with input video signal. For normal use, or not in use, set the pin to Low. 3-level input 12 VDD3 Logic power supply pin (digital) Separate digital VDD from analog VDD. 5.0 ― 13 VDD4 DRAM power supply (digital) Separate digital VDD from analog VDD. 5.0 ― 14 CSYNCIN Composite sync pulse input pin for detecting skew Apply sync separation pulse (positive polarity pulse) of the input video signal. When not in use, set to Low. ― 15 SCL I 2C bus clock input pin ― 16 SDA I 2C bus data input/output pin ― 17 HDPVOUT Sync output pin In Skew Correction Mode: Output can be selected as either HD pulse which is synchronous with output video signal or signal mixed with input PV. In modes other than Skew Correction, drives out C Composite sync pulse. Use for later-stage circuit such as 3DNR. ― 9 20 Ω 20 Ω 11 700 Ω 3.2 V 1.4 V 14 700 Ω 16 700 Ω ACK 15 700 Ω 17 |
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