4304-52 datasheet(8/11 Pages) PEREGRINE

Part #	4304-52

Description	75 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC - 2.0 GHz

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

Direct Link	http://www.peregrine-semi.com

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Product Specification

PE4304

Page 8 of 11

Document No. 70-0066-04

│ UltraCMOS™ RFIC Solutions

Table 7. 6-Bit Attenuator Serial Programming

Register Map

Table 9. Parallel Interface AC Characteristics

Figure 19. Parallel Interface Timing Diagram

Table 8. Serial Interface AC Characteristics

Figure 18. Serial Interface Timing Diagram

LE

Clock

Data

MSB

LSB

t

LESUP

t

SDSUP

t

SDHLD

t

LEPW

B5

B4

B3

B2

B1

B0

C16

C8C4

C2C1

C0.5

↑↑

LSB (last in)

MSB (first in)

Note:

fClk is verified during the functional pattern test. Serial

programming sections of the functional pattern are clocked

at 10 MHz to verify fclk specification.

VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

t

PDSUP

t

PDHLD

Parallel Data

C16:C0.5

LE

t

LEPW

VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

Symbol

Parameter

Min

Max

Unit

fClk

Serial data clock

frequency (Note 1)

10

MHz

tClkH

Serial clock HIGH time

30

ns

tClkL

Serial clock LOW time

30

ns

tLESUP

LE set-up time after last

clock falling edge

10

ns

tLEPW

LE minimum pulse width

30

ns

tSDSUP

Serial data set-up time

before clock rising edge

10

ns

tSDHLD

Serial data hold time

after clock falling edge

10

ns

Symbol

Parameter

Min

Max

Unit

tLEPW

LE minimum pulse width

10

ns

tPDSUP

Data set-up time before

rising edge of LE

10

ns

tPDHLD

Data hold time after

falling edge of LE

10

ns

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