UC62LS4096AI-25 datasheet(1/9 Pages) ETC1

Part #	UC62LS4096AI-25

Description	Low Power CMOS SRAM

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Low Power CMOS SRAM

256K X 16

UC62LS4096

-20/-25

Features:

• Vcc operation voltage :

3.0 V~ 3.6V

• Low power consumption :

20mA (Max.) operating current

2uA (Typ.) CMOS standby current

• High Speed Access time :

25ns (Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Data retention supply voltage as low as 1.2V

• Easy expansion with CE\ and OE\ options

Description

The UC62LS4096 is a high performance, low power

CMOS Static Random Access Memory organized as 262,144

words by 16 and operates from 3.0V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide

both high speed and low power features with a typical CMOS

standby current of 2uA and maximum access time of 25ns in

3.0V operation.

Easy memory expansion is provided enable (CE\), and

active LOW output enable (OE\) and three-state output

drivers.

The UC62LS4096 has an automatic power down feature,

reducing the power consumption significantly when chip is

deselected.

The US62LS4096 is available in the JEDEC standard 44

pin TSOP (Type II) and 48 pin mini-BGA.

PRODUCT FAMILY

Power Consumption

Speed

(ns)

STANDBY

Operating

Product Family

Operating

Tempature

Vcc Range

Vcc=3.0V(Max.)

Vcc=3.3V(Typ.)

Vcc=3.6V(Max.)

Package

Type

UC62LS4096JC

TSOPII-44

UC62LS4096KC

BGA-48

UC62LS4096AC

0

~ 70

℃℃

3.0V ~ 3.6V

20/25

2uA

20mA

DICE

UC62LS4096JI

TSOPII-44

UC62LS4096KI

BGA-48

UC62LS4096AI

-40

~

℃

85℃

3.0V ~ 3.6V

20/25

2uA

20mA

DICE

PIN CONFIGURATIONS

A4

1

A3

2

A2

3

A1

4

A0

5

CE

6

DQ0

7

DQ1

8

DQ2

9

DQ3

10

11

GND

12

DQ4

13

DQ5

14

DQ6

15

DQ7

16

WE

17

A16

18

A15

19

A14

20

A13

21

A12

22

A5

44

A6

43

A7

42

OE

41

UB

40

LB

39

DQ15

38

DQ14

37

DQ13

36

DQ12

35

GND

34

VCC

33

DQ11

32

DQ10

31

DQ9

30

DQ8

29

NC

28

A8

27

A9

26

A10

25

A11

24

A17

23

UC62LS4096JI

LB

OE

A0

A1

A2

NC

DQ8

UB

A3

A4

CE

DQ0

DQ9

DQ10

A5

A6

DQ1

DQ2

GND

DQ11

NC

A7

DQ3

VCC

DQ12

NC

A16

DQ4

GND

DQ14

DQ13

A14

A15

DQ5

DQ6

DQ15

NC

A12

A13

WE

DQ7

NC

A8

A9

A10

A11

A17

VCC

UC62LS4096JC

BLOCK DIAGRAM

MEMORY ARRAY

256K X 16 Bits

COLUMN DECODER

SENSE AMPLIFIER

&

WRITE DRIVER

I/O BUFFER

X16

COL

Address

ROW

Address

CE

WE

OE

CE

WE

OE

DQ0 ~ DQ15

UB

LB

UB

LB

U-Chip Technology Corp. LTD.

Preliminary

Rev.1.0

Reserves the right to modify document contents without notice.

PAGE

1

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