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IDT709269S9PF Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT709269S9PF Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 15 page  6.42 IDT709269S/L Preliminary High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 7 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza- tion, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE) and FT/PIPEX. 4. 'X' in part number indicates power rating (S or L). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office. AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3,4,5) (VCC = 5V ± 10%, TA = 0°C to +70°C) 709269X 9 Com'l Only 709269X 12 Com'l Only 709269X 15 Com'l Only Sym bol Parameter Min.Max.Min.Max. Min.Max. Unit tCY C 1 Clo ck Cycle Tim e (Flo w-Thro ug h)(2) 25 ____ 30 ____ 35 ____ ns tCY C 2 Clo ck Cycle Tim e (P ip e line d )(2) 15 ____ 20 ____ 25 ____ ns tCH1 Clo c k H ig h Tim e (Flo w-Thro ug h)(2) 12 ____ 12 ____ 12 ____ ns tCL 1 Clo c k Lo w Tim e (F lo w-Thro ug h)(2) 12 ____ 12 ____ 12 ____ ns tCH2 Clo c k H igh Time (P ipelined)(2) 6 ____ 8 ____ 10 ____ ns tCL 2 Clo c k Lo w Tim e (P ipelined)(2) 6 ____ 8 ____ 10 ____ ns tR Clo ck Rise Tim e ____ 3 ____ 3 ____ 3ns tF Clo ck F all Tim e ____ 3 ____ 3 ____ 3ns tSA A d dres s S e tup Time 4 ____ 4 ____ 4 ____ ns tHA A d dres s Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tSC Chip E nab le S e tup Tim e 4 ____ 4 ____ 4 ____ ns tHC Chip E nab le Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tSB By te Enab le Se tup Tim e 4 ____ 4 ____ 4 ____ ns tHB By te Enab le Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tSW R/ W Se tup Tim e 4 ____ 4 ____ 4 ____ ns tHW R/ W Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tSD Inp ut Data S e tup Tim e 4 ____ 4 ____ 4 ____ ns tHD Inp ut Data Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tSA D ADS Se tup Tim e 4 ____ 4 ____ 4 ____ ns tHA D ADS Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tSCN CNTEN Se tup Tim e 4 ____ 4 ____ 4 ____ ns tHCN CNTEN Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tSRS T CNTRST Se tup Tim e 4 ____ 4 ____ 4 ____ ns tHRS T CNTRST Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tOE Outp ut E nab le to D ata Valid ____ 12 ____ 12 ____ 15 ns tOL Z Outp ut E nab le to O utp ut Lo w-Z(1) 2 ____ 2 ____ 2 ____ ns tOHZ Outp ut E nab le to O utp ut Hig h-Z(1) 1 7 17 17 ns tCD1 Clo c k to Data Valid (Flo w-Thro ug h)(2) ____ 20 ____ 25 ____ 30 ns tCD2 Clo c k to Data Valid (P ip e line d )(2) ____ 9 ____ 12 ____ 15 ns tDC Data Outp ut H o ld A fte r C lo c k Hig h 2 ____ 2 ____ 2 ____ ns tCK H Z Clo c k H ig h to Outp ut Hig h-Z(1) 2 92929 ns tCKL Z Clo c k H ig h to Outp ut Lo w-Z(1) 2 ____ 2 ____ 2 ____ ns Port-to-P ort Delay tCWD D W rite P o rt Clo c k H ig h to Re ad Data De lay ____ 40 ____ 40 ____ 50 ns tCCS Clo c k -to -Clo c k S e tup Tim e ____ 15 ____ 15 ____ 20 ns 3 493 tb l 11 |
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