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PE4240-EK Datasheet(PDF) 2 Page - Peregrine Semiconductor Corp. |
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PE4240-EK Datasheet(HTML) 2 Page - Peregrine Semiconductor Corp. |
2 / 8 page Product Specification PE4240 Page 2 of 8 ©2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0067-03 │ UltraCMOS™ RFIC Solutions Table 2. Pin Descriptions Table 3. Absolute Maximum Ratings Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 4. DC Electrical Specifications @ 25 °C Notes: 1. A bypass capacitor should be placed as close as possible to the pin. 2. Both RF pins must be held at 0 VAC or require external DC blocking capacitors. 3. The exposed pad must be soldered to the ground plane for proper switch performance. Figure 3. Pin Configuration Table 5. Control Logic Truth Table Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. Exposed Solder Pad - Shorted to Pin 2 (bottom side) RF2 GND RF1 RFC CTRL V DD 4 5 6 3 2 1 Device Description The PE4240 high isolation SPST CATV Switch is designed to support CATV applications such as premium channel service connect/disconnect switch blocks. This function is typically performed by bulky and expensive mechanical switches. The high isolation characteristics (>44 dB at 1 GHz, 85 dB at 5 MHz), high compression point, and an integrated 75-ohm terminations make the PE4240 an ideal, low cost solution. Pin No. Pin Name Description 1 VDD Nominal 3 V supply connection.1 2 GND Ground connection. 3 3 RF1 RF port. 2 4 CTRL CMOS or TTL logic level: High = RF1 to RF2 signal path Low = RF1 isolated from RF2 5 GND Ground connection. 3 6 RF2 RF port. 2 Parameter Min Typ Max Unit VDD Power Supply 2.7 3.0 3.3 V IDD Power Supply Current (VDD = 3V, VCNTL = 3V) 33 40 µA Control Voltage High 70% VDD 5 V Control Voltage Low 0 30% VDD V Symbol Parameter/Condition Min Max Unit VDD Power supply voltage -0.3 4.0 V VI Voltage on CTRL input -0.3 5.5 V TST Storage temperature -65 150 °C TOP Operating temperature -40 85 °C PIN Input power (50Ω), CTRL=1/CTRL=0 33/24 dBm VESD ESD voltage (Human Body Model) 200 V Control Voltage (CTRL) Signal Path (RF1 to RF2) High1 ON Low OFF 2-way Splitter Premium Channel Filter PE4240 PE4240 CATVin CATVout Notes: 1. CTRL accepts both CMOS and TTL voltage leads. The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5- volt logic HIGH signal. (A minimal current will be sourced out of the VDD pin when the control logic in- put voltage level exceeds VDD.) Figure 4. Typical Application Block Diagram |
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