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3342-54 Datasheet(PDF) 3 Page - Peregrine Semiconductor Corp. |
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3342-54 Datasheet(HTML) 3 Page - Peregrine Semiconductor Corp. |
3 / 17 page Product Specification PE3342 Page 3 of 17 Document No. 70-0091-03 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. 18 13 Dout Output Data out function. Dout is defined with the Enhancement Register and enabled with ENH . 19 14 VDD (Note 1) Same as pin 1. 20 15 PD_ D Output Phase detector output. PD_D pulses negatively when fp leads fc. 21 16 PD_ U Output Phase detector output. PD_U pulses negatively when fc leads fp. 22 17 EESel Input Control line for Frequency Register selection, EE Register parallel loading, and EEPROM programming. Internal 70 k Ω pull-up resistor. 23 GND (Note 2) Ground. 24 18 fr Input Reference frequency input. Table 3. DC Electrical Specifications Pin No. TSSOP Pin No. QFN Pin Name Type Description Notes 1: VDD pins 1, 11, and 19 (TSSOP) or pins 6, 14 and 19 (QFN), are connected by diodes and must be supplied with the same positive voltage level. 2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation . Table 2. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units VDD Supply voltage –0.3 +4.0 V VI Voltage on any digital input –0.3 VDD+0.3 V TStg Storage temperature range –65 +85 °C Symbol Parameter/Conditions Min Max Units VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C Symbol Parameter/Conditions Min Max Units VESD ESD voltage human body model (Note 1) 1000 V VESD (VPP) ESD voltage human body model (Note 1) 200 V Note 1: Periodically sampled, not 100% tested. Tested per MIL- STD-883, M3015 C2 Table 4. ESD Ratings Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC and AC Characteristics table. Exposure to absolute maximum ratings for extended periods may affect device reliability. |
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