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3342-34 Datasheet(PDF) 9 Page - Peregrine Semiconductor Corp. |
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3342-34 Datasheet(HTML) 9 Page - Peregrine Semiconductor Corp. |
9 / 17 page Product Specification PE3342 Page 9 of 17 Document No. 70-0091-03 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Enhancement Register The Enhancement Register is a buffered serial shift register, loaded from the Serial Data Port. It activates special test and operating modes in the PLL. The bit assignments for these modes are shown in Table 11. The functions of these Enhancement Register bits are shown in Table 12. A function becomes active when its corresponding bit is set HIGH. Note that bits 1, 2, 5, and 6 direct various data to the Dout pin, and for valid operation no more than one should be set HIGH simultaneously . The Enhancement Register is buffered to prevent inadvertent control changes during serial loading. Data that has been loaded into the register is cap- tured in the buffer and made available to the PLL on the falling edge of E_WR. A separate control line is provided to enable and disable the Enhancement mode. Functions are enabled by taking the ENH control line LOW. Note: The enhancement register bit values are unknown during power up. To avoid enabling the enhancement mode during power up, set the Enh pin high (“1”) until the enhancement register bit values are programmed to a known state. Table 11. Enhancement Register Bit Assignments Reserved EE Register Output fp output Power down Counter load MSEL output fc output Reserved B0 B1 B2 B3 B4 B5 B6 B7 Table 12. Enhancement Register Functions Bit Function Description Bit 0 Reserved Program to 0 Bit 1 EE Register Output Allows the contents of the EE Register to be serially shifted out Dout, LSB (B0) first. Data is shifted on rising edge of Clock. Bit 2 fp output Provides the M counter output at Dout. Bit 3 Power down Powers down all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Provides the internal dual modulus prescaler modulus select (MSEL) at Dout. Bit 6 fc output Provides the R counter output at Dout. Bit 7 Reserved Program to 0 |
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