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3342-03 Datasheet(PDF) 5 Page - Peregrine Semiconductor Corp. |
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3342-03 Datasheet(HTML) 5 Page - Peregrine Semiconductor Corp. |
5 / 17 page Product Specification PE3342 Page 5 of 17 Document No. 70-0091-03 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Max Units Control Interface and Registers (see Figure 4) fClk Serial data clock frequency (Note 1) 10 MHz tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tDSU Data set-up time to Clock rising edge 10 ns tDHLD Data hold time after Clock rising edge 10 ns tPW S_WR pulse width 30 ns tCWR Clock rising edge to S_WR rising edge 30 ns tCE Clock falling edge to E_WR transition 30 ns tWRC S_WR falling edge to Clock rising edge 30 ns tEC E_WR transition to Clock rising edge 30 ns EEPROM Erase/Write Programming (see Figures 5 & 6) tEESU EELoad rising edge to VPP rising edge 500 ns tEEPW VPP pulse width 25 30 ms tVPP VPP pulse rise and fall times (Note 2) 1 µs Main Divider (Including Prescaler) FIn Operating frequency 300 2700 MHz FIn Operating frequency Speed-grade option (Note 3) 300 3000 MHz PFIn Input level range External AC coupling -5 5 dBm Main Divider (Prescaler Bypassed) FIn Operating frequency (Note 4) 50 270 MHz PFIn Input level range External AC coupling (Note 4) -5 5 dBm Reference Divider fr Operating frequency (Note 5) 100 MHz Pfr Reference input power (Note 4) Single ended input -2 dBm Phase Detector fc Comparison frequency (Note 6) 20 MHz SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C) 100 Hz Offset -75 dBc/Hz 1 kHz Offset -85 dBc/Hz Note 1: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk specification. Note 2: Rise and fall times of the VPP programming voltage pulse must be greater than 1 µs. Note 3: The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14, Ordering Information, for ordering details. Note 4: CMOS logic levels can be used to drive FIn input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum frequency limit exists when operated in this mode. Note 5: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. Note 6: Parameter is guaranteed through characterization only and is not tested. |
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